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    PSoC63 Hibernate Current Consumption too high - how to reduce?



      I am setting the PSoC63 into the Hibernate mode with running RTC for wake-up triggering. With a Keysight N6705C power analyzer I measure 4 µA in Hibernate mode. Expected value was 800 nA Hibernate + 380 nA RTC (running with ECO) = 1.18 µA.


      I connect 3 V to the PWR pin (removed jumper j8) on the backside of the PSOC 6 BLE Pioneer board and connect GND of the power analyzer to any GND pin on the board. I looked in the schematics and I dont see any other current drawing device which is connected the the PWR pin. Is this the correct measurement procedure I can do with my power analyzer? I have to use the power analyzer for accurate measurements and do a reliable comaprison to other chips.


      I reduced all LF clocks to the WCO clock and also disabled debugging pins to GPIO and no GPIOs are used at all. I enabled the 0.9 V SIMO buck.


      The project does the following:


      - Wake up from RTC every 3 seconds

      - Advertisement

      - Wait 5 ms for Advertisement done

      - Put system back to hibernate



      Do you have any idea what I could have forgotten to disable? When entering Hibernate mode, do I have to explicitly disable any blocks?


      Thank you!

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