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With the S70FL01GS, you can configure Zynq QSPI as the "Dual SS, 4-bit Stacked I/O" which described in the Xilinx's document (UG585). In this configuration, you should connect MIO0/1 to two chip selects, MIO2-MIO5(QSPI0 IO0-3), and MIO6(QSPI0 CLK). MIO9(QSPI1 CLK) and MIO10-MIO13 (QSPI1 IO0-3) are not used. There is no internal pull-ups on the Chip Selects in the FL01GS so please place external pull-ups.