3 Replies Latest reply on Jul 18, 2018 5:19 AM by srdr

    How to configure a valid output pixel clock in the CX3 MIPI Receiver configuration

    frank.hartmann_3127206

      Hi,

       

      no matter what I do I get a red badge (error/warning) next to Output Pixel Clock in the " CX3 MIPI Receiver configuration" tool.

       

      The currently calculated value is 127.20MHz

       

      The min value is 110.88, The max value is 100. The max value is smaller than the min!

       

      cx3-mipi-receiver-configuration.PNG

       

      Could you please provide guidance how the min&max can be influenced?

        • 1. Re: How to configure a valid output pixel clock in the CX3 MIPI Receiver configuration
          keaj

          Hi,

           

          The minimum value of the output pixel clock is calculated from the input values provided in the "Image Sensor Configuration" tab.

          Please make sure that the values entered are accurate.

          The maximum value of the output pixel clock that the CX3 can support, is fixed to 100MHz.

           

          The MIPI bridge inside the CX3 chip converts the MIPI CSI data to parallel data. In order to send the complete video data over 16-bit parallel interface without any data loss, the minimum PIxel clock required in the parallel interface is 110.88MHz (as per the above screenshot).

           

          As the clock value is higher than what CX3 can support, you should increase the parallel bus width to 24 bit to support the same video bandwidth. This will reduce the clock requirement to 110.88*16/24=  73.92Hz (which is less than 100MHZ).

          • 2. Re: How to configure a valid output pixel clock in the CX3 MIPI Receiver configuration
            frank.hartmann_3127206

            Hi,

             

            does increasing the parallel bus width to 24bits add constraints to the horizontal resolution (e.g. dividable by '3' )?

             

            I followed your advide  (24bit) but the tool is still not happy.

            "Output pixel clock" 60MHz [min: 35.51 | max: 100.00] looks fine, but there is a red 'X' and a popup message 'min:108.06' if i move the mouse to the red 'x'. I could not capture this popup on the screen shot unfortunately. What is the meaning of this?cx3-mipi-24bit-output-video.PNG

            • 3. Re: How to configure a valid output pixel clock in the CX3 MIPI Receiver configuration
              srdr

              Hartmann,

               

              There is a constraint that horizontal resolution should be divisible by 3 (for 24 bytes mode).

              The configuration shown in the scree shot is correct. Please ignore the 'X' mark in this case. This is wrongly indicating by the tool.

               

              Hence,

              The MIPI configiuration of this inputs parameters will be as follows:

              CyU3PMipicsiCfg_t null_RAW8_Resolution0 = 

              {

                  CY_U3P_CSI_DF_RGB888,  /* CyU3PMipicsiDataFormat_t dataFormat */

                  4,                          /* uint8_t numDataLanes */

                  7, /* uint8_t pllPrd */

                  399, /* uint16_t pllFbd */

                  CY_U3P_CSI_PLL_FRS_250_500M, /* CyU3PMipicsiPllClkFrs_t pllFrs */ 

                  CY_U3P_CSI_PLL_CLK_DIV_4, /* CyU3PMipicsiPllClkDiv_t csiRxClkDiv */

                  CY_U3P_CSI_PLL_CLK_DIV_8, /* CyU3PMipicsiPllClkDiv_t parClkDiv */

                  0,                 /* uint16_t mClkCtl */

                  CY_U3P_CSI_PLL_CLK_DIV_2, /* CyU3PMipicsiPllClkDiv_t mClkRefDiv */

                  2046,         /* uint16_t hResolution */

                  0                         /* uint16_t fifoDelay */

              };