3 Replies Latest reply on Jul 27, 2018 3:16 AM by abga

    Input_delay for FX3 at FPGA in AN65974

    peter_birdy_3557726

      Dear all,

      with the cypress FX3 slave fifo implmentation example already comes an FPGA image for altera devices.

      In this example, there is a timing constraints file for setting set_output_delay at the output from FGPA to FX3 GPIF II.

       

      However, set_input_delay is missing form this example. In my loopback project, where I'm using the provided loopback example image for fx3 an for altera FPGA I recognize that sometimes 1 Bit of 32 GPIF data word arrives wrong at the fpga.

      In the pdf for slave fifo implementation there is the timing diagram for read and write transfers for fx3 (see attached images). However I'm not sure what values of it I need to set correct input_delay.

      Altera recommends for input delay:

       

      set_input_delay -max [$period - Tsu]

      set_input_delay -min [Th]

       

      But what are Tsu und Th in the READ from FX3 diagramm???

        • 1. Re: Input_delay for FX3 at FPGA in AN65974
          abga

          Hi Peter,

           

          Tsu : Setup time and Th: Hold time depends on your design and FPGA board. When FPGA is taking data, it has nothing to do with FX3. You can try with 6 ns value to make sure that all the data bits gets settled when clock edge arrives.

          One more solution is, on FPGA side you can sample the data on negative clock edge.

          Is it the same bit which is arriving wrong most of the time?

           

          Thanks & Regards

          Abhinav

          • 2. Re: Input_delay for FX3 at FPGA in AN65974
            peter_birdy_3557726

            Dear Abhinav,

             

            I have set in SDC File:

             

            =================================================================

            set_input_delay  -clock [get_clocks {gclk100}] -add_delay  -max 0.5 [get_ports {dq*}]

            set_input_delay -clock [get_clocks {gclk100}]  -add_delay -min -3.0 [get_ports {dq*}]

             

            set_input_delay -clock [get_clocks {gclk100}] -max $flag_max [get_ports flaga]

            set_input_delay -clock [get_clocks {gclk100}] -min $flag_min [get_ports flaga]

             

             

            set_input_delay -clock [get_clocks {gclk100}] -max $flag_max [get_ports flagb]

            set_input_delay -clock [get_clocks {gclk100}] -min $flag_min [get_ports flagb]

             

             

            set_input_delay -clock [get_clocks {gclk100}] -max $flag_max [get_ports flagc]

            set_input_delay -clock [get_clocks {gclk100}] -min $flag_min [get_ports flagc]

             

             

            set_input_delay -clock [get_clocks {gclk100}] -max $flag_max [get_ports flagd]

            set_input_delay -clock [get_clocks {gclk100}] -min $flag_min [get_ports flagd]

            ================================================================

             

            flag_max is also 0.5 and flag_min is also -3.0. These are the only values where I have wrong data amount of <1%. Deviating from this values causes the design to get nearly 35 % wrong data back to host pc. So I also tried 6ns but then really huge amount of wrong data. The problem lies clearly at the input site: I can tap into the written register at the fpga and it shows at some byte wrong value, but it is most often only one bit (in the near of most significant bit) which is wrong.

            I created a 100 MHz clock at FPGA via PLL. This clock also drives FX3. I just saw that the pll has compensation mode normal but there is the option source synchronous mode. Perhaps this is the mistake?

             

            I attached the project if you want to look into it.

            • 3. Re: Input_delay for FX3 at FPGA in AN65974
              abga

              Hi,

               

              Are you using development boards for FPGA & FX3 or you had designed a custom board. These examples works fine with DVK boards.

               

              If possible could you please probe the Data lines and other interfacing signals. Try to remove all the delays and sample data on the negative edge of the clock.

               

              Thanks & regards

              Abhinav