4 Replies Latest reply on Jul 15, 2018 10:17 PM by vsrs

    The Input Impedance of the SARADC

    user_508813299

      The ADC_SAR_seq Input resistance is specified as 2.2K Ohm max. Is this a series Resistance of the SAR_ADC path or the overall input impedance of the SAR_ADC?

      The low input impedance ADC will limit the application and may require the OP-AMP buffer in the front end.

        • 1. Re: The Input Impedance of the SARADC
          Gyan Chand

          Hello user_508813299 ,

           

              The 2.2 k Ohm is the resistance of the path from a dedicated pin to the SAR ADC input.  Please refer the below document on SAR ADC Design. (Page# 16 on-wards)

           

          http://www.cypress.com/file/141176/download

           

          The low ADC input  impedance problem can be solved either by reducing ADC Sampling Rate or by using the Op-AMP buffer as you mentioned.

           

          -Gyan

          • 2. Re: The Input Impedance of the SARADC
            user_508813299

            Thanks for the prompt reply, Gyan.

             

            I've been asking the same question to Cypress in last few months through the different channel but have received the similar incorrect information.

            I thought it was a very simple question but it seems that I have to explain more detail to get the correct answer - I tried before.

             

            I know the Analog path resistance over the routing path and the sampling speed limitation caused by the R-C filtering effect and it's quite understandable for the programmable part.

             

            What I asked was the input impedance of the PSoC 4 BLE SARADC input as I stated in my original email.

            According to the PSoC5 ADCSAR component datasheet (Cypress doc 001-96049 Rec C) and the PSoC Delta-Sigma ADC Ver3.30 component datasheet (002-22359 REV**), the typical ADC input impedance is 180K Ohm and 74K/148K Ohm respectively.

            In the PSoC 4 SARADC V2.50 component datasheet (002-19123 Rev**), the input resistance is specified as 2.2K Ohm max.

             

            Even though it's defined as the input resistance (not the path resistance) of the ADC spec and no other path resistance definition in the spec, I couldn't believe the value since this low ADC input impedance would undermine the SARMUX function/feature since almost all the application will need the OP-AMP buffer to minimize the loading effect to the measurement point caused by the low ADC input impedance connected to the measurement point.

             

            If this value is true, all the fancy calculations and the expectation of better than 0.01degC temp measurement idea i the App note AN66477 will be wrong even though the differential offset calibration and the accurate current source management control.

             

            But the answers I got was the same each time (2.2K Ohm), I had to design my system using the OP-AMP and the Analog MUX but there was another issue with the Analog Mux in the PSoC Creator (I'll have this issue in the separate thread.) so I've spent lots of time to implement the Analog Mux function through the direct Register control - because of the Analog Mux issue.

             

            Since the program got really complicated to control 11 Analog input signals and the both iDACs, I just tried to check the ADC input impedance by measuring the voltage with the different source impedance before I decide to give up this part for my application and found that the impedance is much higher than 2.2K Ohm.

             

            Now I want Cypress to confirm the actual input impedance of the PSoC 4 SARADC and update the datasheet properly.

            And if I may, I hope Cypress team to pay some more attention to the tech issues brought up by the user so that we can avoid the unnecessary time to find the work around for nothing.

             

            Regards,

             

            KH

            • 3. Re: The Input Impedance of the SARADC
              Gyan Chand

              Hello user_508813299 ,

               

                 The 2.2 K Ohm is the path resistance only ( You can see in the document, I shared ) and not the input impedance of the ADC. The input impedance of ADC  will be very high definitively. However, as you explained , it is not mentioned in the PSoC4 ADC Component datasheet.

               

              -Gyan

              • 4. Re: The Input Impedance of the SARADC
                vsrs

                Hi

                 

                The datasheet value specifies only the routing resistance. The actual input impedance you see from the ADC will be higher than this. It is the routing resistance till the sampling capacitor. The actual resistance due to the sampling capacitor will be some where around  1/(sample rate * 6.4pF).

                 

                 

                Best Regards,
                VSRS