2 Replies Latest reply on Jul 10, 2018 5:13 AM by edward.erns_3346251

    Problem with SPIS Rx Interrupt


      I am using two PSoC 5LP with two different sketches. The first PSoC simulate some SPI-Data-Transfer and the second should receive all Data.
      The RX-Buffer should be cleared by the DMA. The SPIS-Rx-Int. is set on "Interrupt when FIFO not Empty".
      The problem is that the Slave only receive the first Byte (Picture 1) and wont reset the Rx Interrupt (Picture 2).
      My Sketch based on the SPIM/SPIS-DMA example from cypress.


      CH8= DMA_Tx_Master

      CH9= DMA_Rx_Slave



      Did i forget some SPI config?

      Is the timing for the SPIS-Interrupt correct at the 8th clock-rise?

      Is there some kind of SPI-continously-receiving mode?