1: disconnect it from the other MCU, test it.
2: Maximum Total Source or Sink Chip Current 200mA
3: If you only configure part pins as the output status, test it.
4:change the output drive mode, test it.
5: attached your test result.
1- I have some pins that are only connected to test points (not connected to other mcu). I configured them as outputs and get the same behaviour.
2- None of the outputs should source or sink anything close too 200mA.
3- I don't understand what you are suggesting.
4- I have tested the different drive modes and get the same results.
5- No point in attaching other images, the results are the same.
Your 'scope traces are not labeled with the voltage & time scales. Can you share that data with us? Did you mean that you are seeing at 200-250mV (not mA) drop in the GPIO pin output voltage?
I suggest that you examine the power supply pins with your 'scope. It's quite possible that the power supply and/or your bypass capacitors are inadequate for the dynamic load characteristics your circuit is creating. If the power pins show this same or very similar droop, that's you culprit.
Normally a 250mV drop in the high level of a digital CMOS level is not going to exceed the 1 level input specs on a CMOS (or even TTL) level receiver.
I did mean mV instead of mA. Thanks for pointing that out.
I checked the power supply pins on the scope and VDDD, VDD_NS and VDDA all have the same behaviour as the output pins (see attached images of VDDA). The scales should be clearer on the new images, but just in case, it is 100mV on the AC coupled picture and 1V on de DC coupled one both with 25ms on the time scale.
The output of the regulator is steady at 3.3V (before the inductors).
We used the same decoupling as on the pionner kit (same capacitor values and voltage rating). Only the package size is different. We used 0201 and 0402 instead of 0402 and 0603. The temperature coefficient of the capacitors we used is either X5R or X7R.
Could that have an effect?
Given that you have a clean power supply signal on the regulator side of the power supply inductor, and that you see the same noise on the Vdd pins to the PSOC 6 as you see on the high level GPIO pins, it's pretty clear that you have a high current dynamic (switching) load on Vdd. I have not studied the Pioneer kit schematic, so I'm not sure of it's power supply filtering circuitry.
But let's start with some fundamentals that we do know. The scope traces show that you have a high current drain occurring regularly every 30mS and that this drain is lasting for about 5mS. How do these time intervals correlate to whatever software and hardware you have running on the system? For example, do you have a PWM that is running at these rates? Are you doing other I/O at this interval?
Are any other chips using this same Vdd supply? If not, then what ever is drawing the current is being driven by one of the PSOC6 pins. (Otherwise you wouldn't see the Vdd droop here.)
You want to find whatever is drawing this high current and either reduce it, or redesign your circuitry to cause that current drain to come from a different power supply regulator (or at least a different LC filtered branch of the existing regulator).
I also suggest zooming in on these scope traces with a 1-2mS per division timebase and look at the 5mS intervals when Vdd is at it's lowest. It appears from your existing scope photos that this low voltage time interval may include a sequence of multiple, faster noise pulses. Knowing the timing of these might also shed light on what's causing the high current demand.
Another thing to look for is to see if you have any drive fights between I/O pins -- for example on a bidirectional / tristating bus, is one end driving the pin(s) low while the other side is simultaneously driving those pin(s) high?
If these leads don't point you to the cause, and if disabling subsets of your firmware code doesn't give an indication of the source, then I would need to have a broader understanding of your overall system schematic and functional operations.
The dips in the supply voltage seems to be caused by the radio transmission. When not connected, the dips are 30ms apart, which is the advertisement period. Then, when connected, they are about 50ms which is close to the connection interval (48.75ms).
The PSoc6 is on its own regulator. It is handling BLE communication, communication through UART to the other mcu, driving some output pins (going to inputs of the other mcu) and leds.
I don't see this behaviour on the PSoC6 pioneer kit.
Let me know if you think of something else I could test.
OK, that make a good deal of sense. Now it's time to look at your PCB layout. Did you use a 4+ layer PCB, with a layer dedicated to ground and another layer dedicated to Vdd? Excellent signal integrity and supply noise design principles are absolutely necessary to keeping the supplies stable. You also want to be sure that the via placements for your bypass capacitor are properly placed in relationship to the chip power pin traces to minimize via inductance affects. A really good PCB layout is also essential to your eventual need to successfully complete FCC testing and qualification otherwise the unintentional RF emissions will be too high.
If you don't have extensive experience with high speed/high performance digital PCB layout, you will probably want to hire someone to help in this area. Trial and error isn't effective here. :-)
From this response, I know that "The output of the regulator is steady at 3.3V (before the inductors)."
Do you try to remove the inductors and use a zero resistor instead it.
Maybe the unstable is due to the PCB layout.
Ok, I guess I will have to look at the layout this with the rest of the team. This might take a while.
Thanks for your help.
The scopeshot appears like the mux switching (or some periodic loading). Is the mux you are using employs some sort of switch?
The dips appear like the pin is getting loaded by something periodically and the IO drive is not sufficient (typically seen when connecting/disconnecting capacitive loads). You can probably add 10 uF capacitor on the IO and see if the dips reduce/go away to confirm the theory.
Meenakshi Sundaram R
Oops - I skipped all the responses in the discussion (as the question was not answered) Seems like need to do a bit more catch up after my time-off
Could you help us to explain the unstable phenomenon if you have time?