7 Replies Latest reply on Jul 25, 2018 10:35 PM by srnt

    My questions on AN84868 configuring FPGA by FX3

    user_374262161

      My questions on AN84868 configuring FPGA by FX3

      1) In AN84868, if the FPGA has been configured by FX3, it will switch to slave FIFO mode. Does this mean the original codes can only configure FPGA for once? Is it possible to split channels, one channel is only for configuring. If this channel get the data from host, it means the configuration is expected,and the FX3 GPIO switch to configuration.

      2) If the host have not send data to FX3 in AN84868, will the GPIO pins be tristate?

      3) Will the GPIO pins be tristate when the reset pin is hold active.

      The above questions come from my new plan: configuring kintex-7 FPGA by Master BPI mode on powering up and then FX3 can reconfigure FPGA as long as the host sends configuring data, the FX3 should also be in a slave FIFO mode to enable the transfer of data between FPGA and host when not in configuration. BPI and FX3 SPI will share some of FPGA pins. How to avoid conflict?

      Thank you.

        • 1. Re: My questions on AN84868 configuring FPGA by FX3
          srnt

          Hello Maverick Xiang,

           

          - The bin file for the FPGA can be sent over the attached utility more than once. But, for the FPGA to be configured, the configuration data has to be sent to FPGA by holding it in RESET. This can be done connecting a GPIO pin to the FPGA RESET and driving the same.

          - The default state of the GPIO pins after the FX3 device is powered up and after reset is tristate.

          - FX3 SPI writes data to the FPGA only when the host application sends the command. Only under this condition, the Chip Select (CS#) pin of the FPGA is driven by the FX3 SPI. So, there will not be a conflict between the BPI and FX3 SPI.

           

          Please let know if you have further queries.

           

          Best regards,

          Srinath S

          • 2. Re: My questions on AN84868 configuring FPGA by FX3
            user_374262161

            Srinath, thank you.

            As to my knowledge, Xilinx FPGA do not have a RESET pin. Do you mean user defined FPGA RESET pin´╝č Why should I hold this pin active? In AN84868, FX3 first configures its GPIO to configure FPGA, then switches to FIFO transfer mode. Why it can configure FPGA many times? I understand that if FX3 is reset, it can configure FPGA once more, because the firmware is refreshed. If FX3 is not reset, is it able to configure FPGA one more time?

            In AN84868, I do not see a CS pin in SPI GPIO. In FPGA CS# is an output for BPI configuration. No additinal CS# pin exists in FPGA for Slave Serial operation.

            Will the SPI pin for FX3 stay tristated if no data are sent from the host?

            Thank you.

             

            • 3. Re: My questions on AN84868 configuring FPGA by FX3
              srnt

              Hello Maverick Xiang,

               

              - The Xilinx FPGA mentioned in the app note can be made to restart its configuration process when the PROGRAM_B pin is pulled LOW for 500ns or longer.

              - After the configuration process, the FX3 switches to FIFO transfer mode during which the App Note firmware de-initializes the SPI block to re-configure the IO matrix. Hence, the FX3 cannot be used to resend the configuration process. But, the firmware can be modified such that the SPI block is retained without de-initialization and the configuration can be resent over the vendor command.

              - By CS# pin, I meant the SSN (Slave Select) pin of the FX3 SPI block. This pin will be tri-stated when the device is not addressed.

               

              Best regards,

              Srinath S

              • 4. Re: My questions on AN84868 configuring FPGA by FX3
                user_374262161

                In FX3, if SPI_SSN is not asserted, will SPI_MOSI and SPI CLOCK be tristated? If the host does not send configuration data, will SPI_SSN and the other 2 pins be tristated in this application note?

                • 5. Re: My questions on AN84868 configuring FPGA by FX3
                  srnt

                  Hello Maverick Xiang,

                   

                  - When the SPI_SSN is not asserted, the MOSI line will be tri-stated and the SPI CLOCK (SCLK) line will be in its IDLE state.

                  - In the App Note example, after the configuration process is done, the SPI block is de-initialized and the GPIF bus width is set to 32 bit for the slave FIFO operation.

                   

                  Best regards,

                  Srinath S

                  • 6. Re: My questions on AN84868 configuring FPGA by FX3
                    user_374262161

                    Thank you. Is there any proof of your answer “When the SPI_SSN is not asserted, the MOSI line will be tri-stated", in this application note,it is not the truth,because ssn must be asserted and deasserted before sending data to slave FPGA for a proper FPGA configuration.

                    The idle state of sck is not tristated?

                    • 7. Re: My questions on AN84868 configuring FPGA by FX3
                      srnt

                      Hello Maverick Xiang,

                       

                      - Apologies for the confusion. In general, in an SPI transfer, if the SSN line is de-asserted, the data lines are not driven/sampled by the master. But, in case of the app note example firmware, the SPI block of FX3 is only used to serialize the data to be sent over to FPGA. The SPI_SSN line of FX3 is connected to the PROGRAM_B pin of FPGA. This pin is used to asynchronously reset the FPGA and is active LOW. So, the SPI_SSN line of the FX3 is pulled LOW and then released HIGH so as to program the FPGA with the configuration data. In this case, MOSI line is driven with the data when the SPI_SSN line is HIGH (de-asserted).

                      - The idle state of SCK depends on the CPOL. In the app note example, CPOL is set to CyTrue and hence the idle state of SCK is logic HIGH.

                       

                      Best regards,

                      Srinath S