Does the FPGA I2C support I2C SCL clock stretching? When PSoC1 core handling other tasks, it(PSoC I2C Slave) will stretch I2C SCL down for a while and release I2C SCL until those tasks finished.
For more details, refer to: http://www.cypress.com/documentation/application-notes/an50987-getting-started-i2c-psoc-1
Hey , Ryan
Thank you very much for your help.
CY8C9560A-24AXI is an I/O expander. I use a FPGA as the I2C master which supports clock stretching . The SCL should be an unidirectional clock . It's unbelievable that the CY8C9560A-24AXI will pull the SCL down.
And then , The datasheet never mentioned that the CY8C9560A-24AXI will pull the SCL down while being configuring .
Here is the I2C timing from the datasheet.
Thank you all the time.
I saw that , thank you very much.
Do you have any examples of these I2C master which supports clock stretching .
FPGA RTL examples will be best .
Thank you .
Emm...Sorry we don't have FPGA RTL examples. And most I2C master components of PSoC MCU can support I2C slave clock stretching..
For software I2C master, it should monitor I2C bus status and wait until I2C bus released by I2C slave if I2C clock stretch happened...
Thank you all the same.
Could you please tell me when will the I2C bus be released by the slaver.
Is it mentioned in the datasheet?
Thank you .
I've read that topic before.
Thank you, I will try that next.
Thanks a lot.