Serious problems about CY8C9560A-24AXI

Tip / Sign in to post questions, reply, level up, and achieve exciting badges. Know more

cross mob
Anonymous
Not applicable

Hey, Cypress ,

I met a serious problem about  the chip CY8C9560A-24AXI ,

When I tried to access the CY8C9560A-24AXI through my FPGA , The I2C  clock signal was really bad.

As below,

微信图片_20180703095749.jpg

I powered this chip with 3.3V , and also pulled  the SCL/SDA up to 3.3V with 10Kohm   resistors.

But when I tested the signal via oscilloscope, some of the SCL cycles couldn't reach 3.3V .

So ,Why?

Here is my schematic.

捕获.PNG

I need your help , I am looking forward to hear from you as soon as possible.

Best wishes!

Angelic Lea

0 Likes
1 Solution
RyanZhao
Moderator
Moderator
Moderator
250 sign-ins First question asked 750 replies posted

Hi Angelic,

Yes. CY8C9560A-24AXI is an I/O expander and also its internal hardware is same with other PSoC1. 

As the overview says in the datasheet, the I2C slave in this device requires that the I2C master supports clock stretching.

pastedImage_0.png

Thanks,

Ryan

View solution in original post

8 Replies
RyanZhao
Moderator
Moderator
Moderator
250 sign-ins First question asked 750 replies posted

Hi Hao,

Does the FPGA I2C support I2C SCL clock stretching? When PSoC1 core handling other tasks, it(PSoC I2C Slave) will stretch I2C SCL down for a while and release I2C SCL until those tasks finished.

For more details, refer to: http://www.cypress.com/documentation/application-notes/an50987-getting-started-i2c-psoc-1

Thanks,

Ryan 

0 Likes
Anonymous
Not applicable

Hey ,  Ryan

Thank you very much for your help.

CY8C9560A-24AXI   is an  I/O expander.   I use a FPGA as the I2C master which supports clock stretching .  The SCL should be an unidirectional clock .  It's unbelievable  that the CY8C9560A-24AXI  will pull the SCL down.  

And then , The datasheet  never mentioned that  the CY8C9560A-24AXI  will pull the SCL down while being configuring .

Here is the I2C timing from the datasheet.

捕获.PNG

Thank you all  the time.

Angelic

0 Likes
RyanZhao
Moderator
Moderator
Moderator
250 sign-ins First question asked 750 replies posted

Hi Angelic,

Yes. CY8C9560A-24AXI is an I/O expander and also its internal hardware is same with other PSoC1. 

As the overview says in the datasheet, the I2C slave in this device requires that the I2C master supports clock stretching.

pastedImage_0.png

Thanks,

Ryan

Anonymous
Not applicable

Hey, Ryan,

I saw that , thank you very much.

Do you have any examples  of  these I2C master which supports clock stretching .

FPGA RTL examples will be best .

Haha,

Thank you .

0 Likes
RyanZhao
Moderator
Moderator
Moderator
250 sign-ins First question asked 750 replies posted

Emm...Sorry we don't have FPGA RTL examples. And most I2C master components of PSoC MCU can support I2C slave clock stretching..

For software I2C master, it should monitor I2C bus status and wait until I2C bus released by I2C slave if I2C clock stretch happened...

Thanks,

Ryan

0 Likes
Anonymous
Not applicable

Hello, Ryan

Thank you  all the same.

Could you please tell me when will the I2C bus be released by the slaver.

Is it mentioned  in the datasheet?

Thank you .

Angelic

0 Likes
RyanZhao
Moderator
Moderator
Moderator
250 sign-ins First question asked 750 replies posted

Hi Angelic,

Beside the AN50987 mentioned in my first post, here are some more KBAs about the topic.

Clock Stretching and I2C speed

PSoC I2C Block Clock Stretching: Worst Case Duration

Thanks,

Ryan

0 Likes
Anonymous
Not applicable

Hey,Ryan

I've  read that topic before.

Thank you, I will try that next.

Thanks a lot.

best wishes!

Angelic

0 Likes