Excerpt from Cortex™-M0 Devices Generic User Guide
When the processor is executing an exception handler, an
exception can preempt the exception handler if its priority is
higher than the priority of the exception being handled.
When one exception preempts another, the exceptions are called
You cannot "use" ths feature, it is inherant.
The SysTick interrupt priority is configurable.
Please make use of CyIntSetPriority(CY_INT_SYSTICK_IRQN,1) to set the priority of CY_INT_SYSTICK_IRQN to 1. More details are available in PSoC 4 System Reference Guide
OK, it is soltuion for me.
Now i switch from systick to timer2(derived from wco, as ilo is not accurate), as to me the priority of timer2 is unknown, can i set the priority of timer2.
#define CY_INT_NMI_IRQN ( 2u) /* Non Maskable Interrupt */ #define CY_INT_HARD_FAULT_IRQN ( 3u) /* Hard Fault Interrupt */ #define CY_INT_SVCALL_IRQN (11u) /* SV Call Interrupt */ #define CY_INT_PEND_SV_IRQN (14u) /* Pend SV Interrupt */ #define CY_INT_SYSTICK_IRQN (15u) /* System Tick Interrupt */
Please make use of the Interrupts tab to change the priority of interrupt service routines (ISRs) placed in your design. This editor is part of the design wide resources file (cydwr).