HPD IRQ and HPD have defined timing and occurred condition in DisplayPort SPEC. For the signal HPD is HIGH or LOW, the DFP will generate HPD signal as per HPD's status. If HPD IRQ bit status is assert, DFP should follow DisplayPort SPEC generate IRQ plus on HPD signals.
Since you asking those information, I could like to say, if you found IRQ bit is assert, which is equal to the DispalyPort sink have detected DisplayPort source's signal but the signals can not show up on the screen.
w.r.t customized design CCG3 CYPD3120 based dongle logic(UFP) is tightly coupled with display module(we can't do DP plug-in/out, DP lines are routed to DP Receiver pins directly). After USB-C plug-in we will power on this system.
Display module will provide HPD to CYPD-3120 always hope this should not cause problem. What I am expected is, when we plug USB-C to DFP device system will power on and in one of VDM mesage UFP will send attention command and followed by Status message about HPD, status. why UFP is not no able to set HPD IRQ bit.
CYPD 3120 will know HPD input on power on but, why its missing to capture the IRQ bit setting during power on? Will this timing can be modified at application level?
Could you please share your cc log (captured by PD analyzer) and the scope with HPD signals to me? Since CCG3 C to DP firmware have realized IRQ and HPD and reflect to CC message. The two types message will carry HPD information -- DisplayPort Status Updates and Attention.
If IRQ have alreadt shows up, the bit will show up the status.