3 Replies Latest reply on Jun 28, 2018 12:17 AM by holla2040

    Shift Register datasheet question

    holla2040

      Devs,

       

      My understanding is shift registers have a 'value' and 'FIFO'. The value can be read and written by the CPU/DMA. The FIFO is the bit bucket where the shifting occurs on clock. On clock, store transfers FIFO to value and load transfers value to FIFO.

       

      From the ShiftReg 2.30 datasheet,

      "The Shift Register value can be written by the CPU or DMA at any time. The rising edge of the component clock transfers pending FIFO data (previously written by the CPU or DMA) to the Shift Register when the load signal is set. A rising edge of the component clock transfers the current Shift Register value to the FIFO when a rising edge of the optional store input has been detected, where it can later be read by the CPU."

       

      These sentences are confusing. What is "FIFO data" and why/how it was previously written to the FIFO? Should this read

       

      The Shift Register's value can be read or written by the CPU or DMA at any time. When the load signal is set and clock cycles, the Shift Register's value is transferred to the FIFO to be shifted out upon next clock. When the store signal is set and clock cycles, the FIFO is transferred Shift Register's value which can be read at any time.

       

      Is this how it works? I don't know.

       

      Further reading, this is not how it works.

       

      "store – Input * The store input signal triggers the transfer of the current shift register value into the output FIFO."   is this written correctly?

       

      Later it reads, "The ShiftReg_ReadData() API routine can then be used to read the data from the FIFO." . Does ShiftReg_ReadData() get the FIFO or the Shift Register's value?

       

       

      Thanks.

      Craig (confused in Colorado)

        • 1. Re: Shift Register datasheet question
          bob.marlowe

          The ReadData() and WriteData() APIs reads resp. writes from/to the internal 4 items deep FIFO. The corresponding load/store signals do the same independent of CPU intervention.

           

          Bob

          • 2. Re: Shift Register datasheet question
            Gyan Chand

            Hello,

             

                There is one input FIFO {(4 bytes depth) () Writable by CPU/DMA and its value will be written to the shift register on " Load signal asserted  && Rising edge of the clock" } to the shift register and a similar output FIFO ( 4 bytes depth) ( To store the shift registers value on  '''Store' signal asserted && Rising edge of 'clock'")).

             

            Now, you can read/write the value of any of the FIFO as well shift register at any time at the application level by using the respective APIs. ( Refer the datasheet's 'Application Programming Interface' section )

             

            -Gyan

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            • 3. Re: Shift Register datasheet question
              holla2040

              Gyan,

               

              Sounds good, this clears up my confusion. I'll take this and see if I can my shift register example functioning as expected.

               

              Craig