From the description it doesnt sound like a direct connection to FX3 is the best idea, however if that is what is really desired what you could do is find an external PLL to take the ADC clock as input and produce a clock that is 2x of that. So that way the FX3 is running at 100Mhz phase aligned with the original clock. Then at the FX3 just sample the data normally and in software decode CH1 and CH2 because they simply will be alternating Odd samples will be Ch1, Even samples will be CH2 etc.
Or the other way is to have an FPGA or something similar between the FX3 and the ADC.
Edit: Also check out this post GPIF II DDR Mode
Thanks for the tip but I would prefer to go to the DDR approach.
The PLL approach adds more hardware and it seams more prone to get the channels out of sync if there is a cycle slip in the PLL.
Let's see what I can dig on this GPIF II DDR Mode
Is this DDR a true DDR? Does it mean that you can take 2x 32bit per clock cycle at 100MHz? Or do you need to lower the clock frequency to 50MHz?