1 Reply Latest reply on Jun 24, 2018 2:47 PM by Madhu Lakshmipathy

    FX3 - GPIF II, Can i multiplex 32-bit data and 24-bit address on an 8-bit bus from GPIF II to FPGA?

    mzurlo_3526651

      GPIF II - FPGA interface

       

      GPIF is sychronous master 8bit multiplexed address data

       

      Address is 24 bit, data is 32 bit

      Clock can go in either direction

      Output 3 controls signals to FPGA

       

      ALE - address latch enable, asserted low

      DEN - data enable for reads and writes, asserted low

      LWR - local write, high for writes, low for reads

       

      ALE, A[23:16]

      ALE, A[15: 8]

      ALE, A[ 7: 0]

      WAIT - if read operation LWR = 0

      DEN, D[31:24]

      DEN, D[23:16]

      DEN, D[15: 8]

      DEN, D[ 7: 0]

          ..

      Repeat data transactions if burst, address auto increments