Could the NAK be simply timing? I find that a 20mS CyDelay after filling the buffer seems to fix the problem. Is there something I'm supposed to be polling or checking?
FRAM should be fast from what I've read. There might be a pin up-down-up cycling for "finishing" packets, as other inter-chip communications protocols do similar things.
I believe double checking that the pins on the hardware are following the guidelines for the SPI and I2C properly would be worth looking into.
If you are successfully writing to the RAM chip, then the timing should be close if not correct (imo).
Depending on what your I2C to SPI chip is doing, there might be a buffered delay to responses and requests, so try reading multiple times?
Once again, a _very_ careful reading of the documentation might have helped. I did not have the sequence correct. For this part, the write protect needs to be disabled, write needs to be enabled, and then data can go across.
Mea culpa. Thanks to Mr Pratt for replying and thanks to anybody else who at least read my question.