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In FX3 GPIF II, the flags will indicate the status of buffer. It can be either the buffer is full and buffer is empty.
Assume that there are two DMA channels: 1) USB (Producer socket) -> GPIF II (Consumer socket) 2) GPIF II (Producer socket) -> USB (Consumer socket). Each Channel has some buffer space (for example: 4 buffers of 16KB = 64 KB buffer space for channel)
There is a FPGA connected to Slave Fifo interface (GPIF II). The FPGA can write the data to GPIF II and read the data from GPIF II.
Case 1: FPGA writing the data to Slave Fifo
Note that there is a time delay to switch the buffers. so that the FPGA should know that when the buffer is full and stop writing the data to GPIF II until the next buffer is available. And also there is no buffer available to store the data (All are full).
The status of buffer will indicate through the flag. Hence, the FPGA should monitore this flag before writing the data.
Case 2: FPGA read the data from Slave Fifo
Note that there is a time delay to switch the buffers. so that the FPGA should know that when the buffer is empty and stop reading the data to GPIF II until the next buffer is available to read. And also there is no data available to read (All are empty).
The status of buffer will indicate through the flag.
There are two types of flags:
1. Dedicated Thread Flags
a. Dedicated Ready Flag
b. Dedicated Water Mark/ Partial Flag
2. Current Thread Flag
a. Current Ready Flag
b. Current Water Mark/ Partial Flag
1. Dedicated Thread Flag:
Read the thread section to understand what is thread. If we use the Dedicated flag, the staus of buffer is always updated to this flag.
a. Dedicated Ready Flag: This flag will be asserted when there is buffer full and buffer empty (based on the selected thread (socket)).
What if you want to know when the buffer is half full (Writing to GPIF) and half empty (reading from GPIF) OR 3/4 full and 3/4 empty OR any other specific requirement?
GPIF II gives the feasiblity of this requirement through Water Mark Flag. We need to configure the water mark value based on our requiremet. Use the formulas mentioned in the AN65974 to configure them and use CyU3PGpifSocketConfigure() API.
2. Current Thread Flag:
We know that GPIF II has 32 sockets and four threads. Each thread associate to 8 sockets. When you use more than four threads, you can not use dedicated flags. So you should go for current thread flag.
Here, each thread will be selected dynamically and read the status of the flag.
I didn't make myself clear。In fact ,i want to know the meaning of "watremark value".I had read AN65974.It says "
A flag can be configured to indicate the partially empty/full status of a socket. A watermark value must be selected
such that the flag is asserted when the number of 32-bit words that may be read or written is less than or equal to the
"可对标志进行配置，以指示套接字的一部分空/一部分满状态。必须选择满足下面条件的水印值：当将要读/写的 32 位字数低于或等于该水印值时，将激活标志。".
Let's say that 1k of space buffer, if I set the watermark value =4, does that mean that if I read/write less than or equal to 4 bytes, the flag is set。
Have you referred section 8.3 and 8.4 of the App Note?
The configuration of watermark value is explained through the examples (in case of read&write, and 16-bit & 32-bit data bus).
Please go through them.
In the cyfxslfifosync.c of AN65974 ,I saw
Both watervalue were set to 6.Why did they set to 6?It on what basis?whether I can set to others value?
In the 8.3 and 8.4 of the App Note,
the number of data words that may be written after the clock edge at which the partial flag is sampled low =
watermark x (32/bus width) – 4,
Firstly, we can know he number of data words or watermark we can known?
And it on what basis?
USB 3.0,For loopback transfers in the AN65974,the watervalue is set to 6.
For writing to socket_0,whether it means when any buffer had been writeen arrived to 1018,the flagb was set.
For reading from socket_3,whether it means when any buffer had been read arrived 1018,there were only 6 bytes spaceses remained,the flagd was set.
CyU3PGpifSocketConfigure API is used to configure the water mark value that will be used in this calculation: watermark x (32/bus width) – 4.
Say that bus width is 16-bit,
So the number of words (here it refers to 16 bit) that may be written after the clock edge at which the partial flag is sampled low = 6*(32/16) - 4 = 8 16-bit words. i.e The SLWR control signal will be asserted upto 8 clocks and then it should goes to de-asserted state.
In example 3, section 8.4.3 of AN65974, the water mark value is set to 3. Therefore, the number of words that may be written after the clock edge at which the partial flag is sample low is 3* (32/16)-4 = 2 16-bit words. You can see in Figure 13. that the SLWR signal is de-asserted after the two clock cycles from the point where the partial flag (FLAG_B) goes low.
Bottom line: Configure the water mark value and find the number of words (bus width) that can be write to FX3 after the partial flag goes low using the formula watermark x (32/bus width) – 4. Ensure that the FPGA de-assets SLWR line after [watermark x (32/bus width) – 4] cycles from the point where the partial flag goes low.