5 Replies Latest reply on Jun 20, 2018 1:16 AM by BacemD_61

    Parallel NOR Flash Programming Issue

      Dear Sir / Madam,

       

      Following are the part numbers for the Parallel NOR Flash:

      Earlier MPN: S29GL512T10FHI020 (GL-T) -> 45nm

      Current MPN: S29GL01GS11DHI020 (GL-S) -> 65nm

       

      Processor used is PC205 (Pico-Chip).

       

      We are getting “timeout” error while programming using PEEDI JTAG programmer for the Current MPN. Pls find attached image of the error. We can't write to higher than 64MB and the processor can support up to 128MB.

       

      Earlier MPN worked till now without any problems for more than 50 boards.

       

      We used the Current MPN because of availability (lead-time issue of Earlier MPN).

       

      We tried flashing through the U-Boot also & found errors (JFFS2 error) during booting.

       

      Our embedded team found out that accessing greater than 64MB from linux kernel is having some issues.

       

      So, waiting for a solution from your end at the earliest.

       

      Regards,

      Pravardhan U.S

        • 1. Re: Parallel NOR Flash Programming Issue
          BacemD_61

          Hello,

           

          Were you using GL-S and then migrated to GL-T or the opposite? The GL-T is newer than GL-S.

           

          The u-boot version 1.3.4 is a very old version and it may have bugs and limitations whenused with new pNOR flashes. It was released in August 2008.

          We recommend that you use a newer u-boot version. The same statement should apply to Linux if you're using a very old version.

          To get a better understanding of the issue you're having, you may enable the macro DEBUG in the module cfi_flash.c:

           

          #define DEBUG

          git.denx.de Git - u-boot.git/blob - drivers/mtd/cfi_flash.c

           

          You may also define the debug messages by adding the following line at the very beginning of the same module:

          #define debug printf

           

          Best regards,

          Bacem Daassi

          ----

          Cypress semiconductor Corp.

          Customer Applications Engineering

          • 2. Re: Parallel NOR Flash Programming Issue

            HI Bacem Daassi,

             

            Thanks for the reply.

             

            First we used GL-T and then migrated to GL-S.

             

            Regarding the U-Boot, Linux kernel version & enabling DEBUG in cfi flash module, I have forwarded your reply to the embedded team.

             

            Thanks & Regards,
            Pravardhan U.S
            Senior Engineer - Hardware Systems
            Lekha Wireless Solutions

            • 3. Re: Parallel NOR Flash Programming Issue
              BacemD_61

              Hello,

               

              Please also check the following migration guide for more details about the differences between the two products:

              http://www.cypress.com/file/198206/download

              Please also check the higher address pin connection, it's A25 in your case.

              This pin should of course not be left floating and please make sure the controller is driving it correctly.

               

              Best regards,

              Bacem

              • 4. Re: Parallel NOR Flash Programming Issue

                Hi Bacem Daassi,

                 

                Regarding the address A25, it was left floating on the board. So, we soldered a small wire to the A25 (ball no. G8) from both the parallel NOR flash to GND and tried flashing from the PEEDI JTAG programmer and it crossed sector 257 and fully programmed the flash without any error.

                 

                We tried this method in two more boards and they are flashing properly.

                 

                But we still have one question: How could the pNOR flash worked properly up to 64MB but couldn't access higher than 64MB with A25 left floating?

                 

                Thanks & Regards,

                Pravardhan U.S

                • 5. Re: Parallel NOR Flash Programming Issue
                  BacemD_61

                  Hello,

                   

                  Glad to hear that the issue is now solved!

                  The A25 address pin level had a logical low level and was seen by the flash as being low (0), although it was floating.

                  That's why it worked with the lower half.

                  Please also note that the address pin A25 should be connected to the controller and not grounded. Otherwise you will only have access to the lower half the flash.

                   

                  Best regards,

                  Bacem