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Would you please tell why you connect J6.3 (I2S0_MCK) ,J6.6 (I2S0_WS_LRCLK) with the same pin J1.14 (FSYNC) ?
if fs clock is 48khz, the I2S0_MCK might be 256fs or 384fs, I2S0_WS_LRCLK = fs , so may need your help to explain FSYNC ,thanks.
Thanks for your reply. I made a mistake in my previous table, so here is the updated table. I have attached the schematic for the AUDBOOST as well. Please let me know if this makes sense.
J9.4 (3v3, 3.3V power)
J6.3 (I2S0_MCK) and J6.5 (I2S0_SCK_BCLK) should have different clock setting, Are you sure you will connect them together ?
Thanks for you response. I found from TLV320AIC3254 Application Reference Guide (page 5) that just connecting the BCLK is good enough as "The BCLK pin can drive the PLL, Codec Clock and audio interface bit clock inputs simultaneously" where as "The MCLK pin can drive the PLL and Codec Clock inputs simultaneously". So looks like I don't need to connect the MCLK pin.
I think you got the answer, thanks.
Thank you so much for all your help.