2 Replies Latest reply on Jun 14, 2018 12:44 AM by srdr

    Flag Problem in FX3. FLAG A and B always high in beginning

    hendrik2k1_3498761

      Dear all,

      I'm using CYUSB3KIT-003 FX3 as a slave FIFO with 32 bit data word and 100 MHz clock sourced from an external FPGA as application processing unit.

       

      I'm new to this so I tried the from cypress provided examples in AN 65974.

      I'm aware that cypress provided different firmware images for loopback, short-packet, streamIn and streamOut and the correlated fpga images.

       

      When setting up loopback image in fx3 und FPGA and sending data from the control center into the out endpoint I can see the arrival of data in the fpga via Altera Signal Tap Tool. (See attached image).

      FLAG A and B are set High in the beginning and stays high to cause the fpga state machine to get into the loop_back_write state for writing the data back to FX3. This is quite understandable in regard to loopback function.

       

      I want to set up my own control state machine in fpga which can handle stream in and stream out. The fpga example from cypress provide two different fpga images for streaming data in and out. To create one fpga image which can handle both requests I would combine the state machines and would look in the idle state if either flag A and B or flag C and D are set to stream data out and in respectively (and using stremain/out firmware in FX3) However in the beginning Flag A and B are always High (so output buffer in FX3 is not full) and fpga starts to transfer data even when I didn't call XferData with appropiate endpoint. Sometimes I see only flag A is high but not flag B with streamin/out FX3 firmware image.

       

      How is FX3 and/or the fpga statemachine to be configured to only read and write data when user calls api XferData at software on Host-PC?

      The reason for this is, that I want to transfer a definite amount of critical data to fpga and send the calculated new data (fixed amount) back via XferData calls. It should not be a continous streaming. Are flags A B C D the correct indication for the fpga to know if it has to send or receive data?

        • 1. Re: Flag Problem in FX3. FLAG A and B always high in beginning
          hendrik2k1_3498761

          So in other words, I wonder if FLAG A and FLAG B should be inverted?

          I cannot get my head around what is causing the direct write cycle after read cycle without I'm calling for data in Control Center!?

          • 2. Re: Flag Problem in FX3. FLAG A and B always high in beginning
            srdr

            Peter,

             

            1. The XferData's responsibility is to send the IN/OUT reuests to get/send the data from/to the Endpoint. These requests will reach to the endpoint, then the endpoint will respond based on the available data/space to send or receive the data.

            XferData does not have any control over the FX3 functionality as you expected.

             

            So if you are sending a data to FX3 over OUT Endpoint, the data will be send to the FPGA, if the buffer is full. Then FPGA process the data and write back to FX3. This data can be received in PC over the IN end point.

             

            But you are thinking that the data should not received by the FX3 from the FPGA and send to the PC until you do IN transfer in control center. This is incorrect.

             

            -------------------------------------------------------------------------------------

            Note that the DMA buffer will be committed to consumer side, if 1) the buffer is full. 2) buffer is partial full (data size is not multiple of 1024 bytes in SS) 3) Buffer is partial full (data size is mutilple of 1024 bytes and zero length packet )

            -----------------------------------------------------------------------------------

             

            2. When you start the GPIF State Machine, the flag will be set as per the data/space in the associate buffers. Since the FPGA is a Master, it has whole control to write to the FX3 and read from it. The FPGA has to check the Flags behavior and take necessary action.

             

            3. As per your requirement, the PC will send the data to FX3 using XferData over OUT endpoint then this data should be send to the FPGA. Then the FPGA will process it and send it back to FX3. Later, you will send the XferData to IN Endpoint to get the processed data.

             

            What is the amount of data that you are sending to the FX3 over OUTendpoint from the PC?

            What is your buffer size of the DMA Channel created from USB Producer socket to GPIF Consumer Socket?

             

            4. Note that there are two kinds of flags: Dedicated Flags and Partial Flags.

            In AN65974, FlagA and FlagC are dedicated flags; Flag B and Flag D are partial Flags. Read the App Note for more details on the Flags.