Can you please provide us with the schematics of the SRAM portion for your application.
1 Set the address to ADDR / DAT_2-17
2 DD4 and DD5 Latches hold the address and feed it to DS1 and DS2
3 Remove the address ADDR/DAT_2-17
4 DD4 and DD5 Latches continue to hold the address and feed it to DS1 and DS2
5 give the command to read DS1 and DS2, at the address that holds DD4 and DD5
6 If the number of " 1 " in the data exceeds ~70%, the effect of Latch up is observed. There is a current surge up to 12A
ОЗУ 8bit.PDF 355.0 K
Hi White Leo,
We are not aware of any such issues with our devices (consuming a high current (12A) during read operation). We would like to get some more details about this issue?
1. Are you observing this issue with all of the boards that you tested? Or, is it with only one board?
2. If it is with only one board, can you replace the SRAMs on that board with new ones and check if the issue happen again?
3. Are the IO lines shared between any other devices?
4. Are you observing such high current consumption during write operation also?
Thanks and Regards,