5 Replies Latest reply on Jul 1, 2018 6:12 AM by user_247090680

    Howto minimize current consumption during cold-boot!?

    user_247090680

      Hi,

       

      I'm using a PSoC 4L running of 1.8V.

      • power-scheme: 5V (with soft-start / will "ramp up") -> Buck to 4.2V "SYS" -> LDO -> 1.8V
      • the supply has a ~200mS delay before the 4.2V rail will be live, before that, SYS can be about 1.5V

       

      Issue:

      • seems like the psoc is drawing about 2-3mA immediately, even at 1.5V supply...
        • Can I assume that it's drawing this while waiting for 1.72V+ VDD so it can start properly?
      • Once the PSoC starts, would it be possible to achieve <= 1 mA current draw during a say 100mS period?

       

       

      Thanks

      David

        • 1. Re: Howto minimize current consumption during cold-boot!?
          e.pratt_1639216

          When in an indeterminate wakeup/power state, the chip will draw "active" current I believe. This will be 2-3 mA if you have the chip power settings setup to use more clocks/hardware.

           

          Once the PSoC starts, you can put it into Sleep/DeepSleep modes which will use low power (uA's worth). You can setup a hardware timer to end the low power mode after 100 ms.

          • 2. Re: Howto minimize current consumption during cold-boot!?
            xzng

            Q: Can I assume that it's drawing this while waiting for 1.72V+ VDD so it can start properly?

            A: Yes, When VDD ramp up to 0.8V~1.45V, internal POR circuit is triggered and keeps silicon in reset status, this internal reset signal won't  release until silicon is correctly powered (VDD ramp up above 1.71V).

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            • 3. Re: Howto minimize current consumption during cold-boot!?
              user_247090680

              Exactly, the rail ramps over about 70-80ms from 0V to 1.80V

               

              so the question is, what's the current draw

              - up to 0.8V ?

              - from 1.45V to 1.72V ?

               

              /d

              • 4. Re: Howto minimize current consumption during cold-boot!?
                xzng

                David,

                 

                We don't have so detailed current data about silicon booting up, even in internal doc i cannot find any data about this.  I tested the current draw by using digital regulator and CY8CKIT-046 DVK(PSoC4 L DVK) by my self, for your refer:

                 

                VDDD/VDDA          Current

                0.8 V                         6.4 uA

                0.9 V                         25.2 uA

                1.0 V                         86.6 uA

                1.1 V                         204 uA

                1.2 V                         496 uA

                1.3 V                         704 uA

                1.4 V                         861 uA

                1.5 V                         1.04 mA

                1.6 V                         1.94 mA

                1.69 V~1.7 V             3.43 mA

                >= 1.7V                     POR Release Reset, CPU enter Main()         

                 

                If PSoC draw 2-3mA current at 1.5V supply on your board, maybe this current is not only drew by PSoC.

                 

                Regards

                Vison         

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                • 5. Re: Howto minimize current consumption during cold-boot!?
                  user_247090680

                  much appreciated Vision, thanks fo measuring this.