2 Replies Latest reply on Jul 10, 2019 11:19 PM by LinglingG_46

    Psoc6 SRAM retention


      Hi All:

           About Psoc6 SRAM retention in the DS mode,I have some questions to ask:

         1:If I want to  the only 64K SRAM retention in in the DS mode,which mode should I set ,the "RETAINED MODE"?And if  I set the PWR_MODE control bit to the 0x02 after the power up,the SARM can use  normal or not? Should I set the PWR_MODE control bit to the 0x03 after the wake up event happened ?
          2: The SARM can't be used by the user if  I set the PWR_MODE control bit to the 0x00 after the power up.Is that right?

        • 1. Re: Psoc6 SRAM retention



          To your questions,


          1) If you want only 64 K (or 2 blocks) of SRAM, then you will need to disable/power down the remaining 7 blocks (224 KB) of SRAM by setting the PWR_MODE bits to 0. By default all SRAM blocks are enabled on power up. If SRAM is enabled (or in retention), it enters retention when the system enters deep sleep. Only when it is disabled, its power is cut-off and the data will be lost and it becomes not accessible to the user. Having said that, in order for the device to use only 64 KB of SRAM, you will need to modify your linker scripts (for both CM0+ and CM4). Make sure you allocate RAM to cores in the blocks that you intend to keep enabled. Let me know if you need help with that.


          2) Yes that is correct. Just remember each 32-KB block (CPUSS->RAM0_PWR_MACRO_CTL[i]) has its own PWR_MODE bits and hence only those 32-KB blocks which has the PWR_MODE bits set to 0 will not be accessible.



          Meenakshi Sundaram R

          • 2. Re: Psoc6 SRAM retention

            I use the below codes to test, but I don't find any change on the chip power consumption compared with use

            " Cy_SysPm_DeepSleep(CY_SYSPM_WAIT_FOR_INTERRUPT);"


            __enable_irq(); /* Enable global interrupts. */

            #if (SLEEP == CM4_POWER_MODE)

            #elif (DEEPSLEEP == CM4_POWER_MODE)
                for(int32 i =1; i<9;i++){
                   test[i] = CPUSS->RAM0_PWR_MACRO_CTL[i]; //= 0x05FA0000;
                CPUSS->RAM1_PWR_CTL= 0x05FA0000;
                CPUSS->RAM2_PWR_CTL= 0x05FA0000;


            #elif (HIBERINATE == CM0_POWER_MODE)