9 Replies Latest reply on May 31, 2018 11:01 PM by rajiv.vasanth.badiger

    SR Flip Flop weirdness

    mikeboich_1580576

      I have a fairly complex project that uses a PSOC to control a CRT vector display.  I recently started having trouble with a section that previously worked as expected.  I've tracked it down to an SR flipflop that seems to not behave properly.  I've deleted everything else in the project, so the attached project is just a flip flop with a constant 1 level on the S input and a constant 0 level on the R input.  The output of the FF is fed to an AND gate with a constant one on its other input.  The pin which is driven by the AND gate shows zero, which suggests that the FF is outputting zero.  If I change the gate to an OR gate, the pin outputs one, as you would expect. (So the pin appears to work properly.)  Can anybody tell me what's happening here?  If I completely recreate this in a brand new project, it works properly, which is nice to know, but I'm hoping I don't have to recreate my entire project.  Perhaps that's the answer though.  Does this "project rot" occur in PSOC?

       

      Thanks in advance for any answers.

       

      - Mike