2 Replies Latest reply on May 29, 2018 2:39 AM by villanueva.jos_3207616

Offset in some DQ bits of the FX3 (CYUSB3KIT-003)

villanueva.jos_3207616 May 25, 2018 9:26 AM

Hi, I'm using CYUSB3KIT-003 and I implemented the syncronous Slave with state machine of the AN65974 example (32bits). The problem is with some bits of the GPIF II have an offset around 1.2V and the FPGA can't detect the zero level. For some reasons it is influenced with the presence of the watermark flag. The bits afected isn't the same with another FX3.

Do you have any idea what is going on?

1. Re: Offset in some DQ bits of the FX3 (CYUSB3KIT-003)

villanueva.jos_3207616 May 26, 2018 12:28 PM (in response to villanueva.jos_3207616)

Some details: The master is a FPGA, It reads data from FX3 using the DMA_ready flag. At the moment it's only a reading test. The FPGA reads "correctly" with an offset in some bits.
Like Show 0 Likes(0)

Actions
2. Re: Offset in some DQ bits of the FX3 (CYUSB3KIT-003)

villanueva.jos_3207616 May 29, 2018 2:39 AM (in response to villanueva.jos_3207616)

I removed the J5 jumper and all signal are correct. So it is recomended not connect the jumper if don't work with the SRAM
Like Show 0 Likes(0)

Actions

Go to original post