2 Replies Latest reply on May 30, 2018 9:22 AM by jascc_3442861

    S25FL256S - RDSR1 0xFF after BE or 4SE first, then reads correctly

      We recently switched a board from the S25FL512S to the S25FL256S / 256kbit sector option, and have noticed that after a Bulk Erase or 4SE command, the flash will respond to a RDSR1 command with all bits set the first time, and then subsequent reads of RDSR1 will correctly show the WIP bit and write success, error bits will be 0 etc. We never saw this on the S25FL512S, code is basically the same.


      Inserting a few (2-3) dummy reads of RDSR1 seems to be working as a work around, we're able to poll WIP after the first dummy read.


      Is it normal to sometimes read the status register as all bits set / will the flash not drive the status register bits sometimes (we do have 1k pullups on MISO)? Is there a minimum wait time between bulk erase and polling RDSR1? SPI frequency is 2.5MHz, both mode 0 and mode 3 act the same. Flash is factory default settings afaik.