I checked document, #001-13670 EZ-USB Technical Reference Manual.
I am question about Figure 9-1 at see page 99.
Could you tell me FPGA can read data from the CPU EP0?
I understand for readable EPx is EP2, EP4, EP6, EP8.
Hello Hiroki Yamashita-san,
Generally, the FPGA gets interfaced to the FX2LP over the slave FIFO interface. Under this situation, only the endpoints EP2, EP4, EP6, EP8 are accessible by the FPGA.