11 Replies Latest reply on May 24, 2018 12:27 PM by tn49179_3003661

    Filtering digital signal

    tn49179_3003661
    tn49179_3003661 May 22, 2018 6:21 AM

      Hi,

      I'm using CY8CKIT-048 PSoC Analog Coprocessor Pioneer Kit and I am trying to make an FSK demodulator. I tried implementing the demodulator by following and modifying AN2336 made for PSoC1, but I run into problems when I want to filter correlator output signal.

      I attached my project so you can check it out.

      I am generating a sine wave test signal using PWM, DMA and VDAC. Sine wave table and generated sine wave frequencies are set up so that I should get a capital letter 'U' at demodulator output. That signal is connected to a comparator. Comparator output signal is routed into SmartI/O component in which I implemented a shift register. XORing original signal and signal delayed using a shift register should give me an output of high or low duty cycle, based on the frequency of the sine wave, and that signal should be connected to UART and UART should sent that data to my pc where I can see the output data of demodulator in a terminal. But that correlator output signal has some pulses i would like to iron out because I don't get good enough results. I attached a screenshot from the oscilloscope so you can see what I mean. Yellow channel is the signal I need to iron out.

      How do I filter these pulses out? This PSoC doesn't have any digital filtering or glitch filter components as far as I know.

       

      Thanks,

      Tomislav

        • 2. Re: Filtering digital signal
          seg
          seg May 22, 2018 10:13 AM (in response to tn49179_3003661)

          Tomislav:

          The output of the correlator is a duty cycle, low at one frequency, high at the other. To recover the data, put a simple RC low-pass filter from the correlator output to the comparator input. Set the time constant for about 300 usec. In AN2336, we had more analog blocks, so it was all done inside the chip. PSoC Analog Coprocessor does not have as much analog resources so it takes a few external parts. The comparator is made out of one of the opamps, not the low-power comparator. It should have about 10% hysteresis. The filtered signal should drive the inverting input of the comparator. The non-inverting input of the comparator should be connected to AGND (Vdd/2). You can also implement this with a digital filter, but the penny's worth of R and C makes an easy choice to me.

          ---- Dennis

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          • 3. Re: Filtering digital signal
            tn49179_3003661
            tn49179_3003661 May 22, 2018 12:41 PM (in response to seg)

            Thanks for the suggestions, but I forgot to mention that this should be made as a single-chip solution, without adding any external components if it's not necessary. I tried filtering it in software by taking multiple samples of the correlator output in regular time intervals, but output depends on the time when i read correlator output and demodulator output can be completely wrong or completely right depending on timing.

            Is there any other way to filter this signal without using an external RC filter?

            • 4. Re: Filtering digital signal
              odissey1
              odissey1 May 22, 2018 1:41 PM (in response to tn49179_3003661)

              Tomislav,

              If your project still has PDL or UDB resources available, it is possible to average digital stream using hardware filters. See two different examples, utilizing IIR (PLD) or SINC (UDB) filters

              Interfacing iso. ADC like AD74XX

              /odissey1

              • 5. Re: Filtering digital signal
                tn49179_3003661
                tn49179_3003661 May 22, 2018 3:09 PM (in response to odissey1)

                I don't have enough resources available to import these components

                • 6. Re: Filtering digital signal
                  seg
                  seg May 22, 2018 4:06 PM (in response to tn49179_3003661)

                  I'm working on a simple software filter, give me a day or three.

                  ---- Dennis

                  1 of 1 people found this helpful
                  • 7. Re: Filtering digital signal
                    odissey1
                    odissey1 May 22, 2018 11:26 PM (in response to tn49179_3003661)

                    LPFilter component: to minimize PLD consumption, reduce output width to 1 and decrement (~3). That will help, afterwards, you only need to filter a Boolean input to a Boolean output. Sampling clock should be ~4x main frequency.

                    /odissey1

                    • 8. Re: Filtering digital signal
                      tn49179_3003661
                      tn49179_3003661 May 23, 2018 3:35 AM (in response to odissey1)

                      I tried adding the component and setting it up like you said, but it exceeds basically all available psoc resources so it won't even build.

                      • 9. Re: Filtering digital signal
                        user_49271930
                        user_49271930 May 23, 2018 4:21 AM (in response to tn49179_3003661)

                        Perhaps you can help increase the hysteresis.Comp.JPG

                        • 10. Re: Filtering digital signal
                          seg
                          seg May 24, 2018 9:24 AM (in response to user_49271930)

                          Filtering the digital signal is not hard. l built an excel model based on observing your operating frequencies, 5 kHz and 10 kHz.

                          Time base in usec.

                          Trace 1 is modulating data

                          Trace 2 is FSK signal

                          Trace 3 is delayed FSK signal

                          Trace 4 is XOR of 2 and 3, what you want to filter. The duty cycle changing with delay is obvious.

                          Trace 5 is an RC-filtered version (done here with a software IIR filter)

                          The comparator is sampled every 20 usec (set up a timer interrupt to do this)

                          Set up a software counter. When comp out = 1, and count < 32, increment counter.

                          When comp out = 0, and count not equal 0, decrement counter.

                          Trace 6 is the counter result.

                          Set comparison at mid-scale (16). If count > 16 set output high, if <16 set output low.

                          Write output to a pin, connect pin to UART.

                          The interrupt load is minimal, it takes only a few instructions, maybe on a few percent interrupt load.

                          You can easily add hysteresis.

                          Another issue: You waveform looks terrible at the higher frequency:

                          It looks like your sine table is not aligned properly,

                          1 of 1 people found this helpful
                          • 11. Re: Filtering digital signal
                            tn49179_3003661
                            tn49179_3003661 May 24, 2018 12:27 PM (in response to seg)

                            Thank you very much,

                            I'll try to set up the project tonight so I can check it out tomorrow.

                            And I noticed that my sine wave looks bad, but comparator and correlator output seemed fine so I didn't bother changing it. I'm only using sine wave generator for testing the demodulator and I'll remove that part once I get everything else working correctly.