Filtering digital signal

Check also AN60594,

http://www.cypress.com/documentation/application-notes/an60594-psoc-3-and-psoc-5lp-low-frequency-fsk-modulation-and

Tomislav:

The output of the correlator is a duty cycle, low at one frequency, high at the other. To recover the data, put a simple RC low-pass filter from the correlator output to the comparator input. Set the time constant for about 300 usec. In AN2336, we had more analog blocks, so it was all done inside the chip. PSoC Analog Coprocessor does not have as much analog resources so it takes a few external parts. The comparator is made out of one of the opamps, not the low-power comparator. It should have about 10% hysteresis. The filtered signal should drive the inverting input of the comparator. The non-inverting input of the comparator should be connected to AGND (Vdd/2). You can also implement this with a digital filter, but the penny's worth of R and C makes an easy choice to me.

---- Dennis

Tomislav,

If your project still has PDL or UDB resources available, it is possible to average digital stream using hardware filters. See two different examples, utilizing IIR (PLD) or SINC (UDB) filters

Interfacing iso. ADC like AD74XX

/odissey1

I'm working on a simple software filter, give me a day or three.

---- Dennis

LPFilter component: to minimize PLD consumption, reduce output width to 1 and decrement (~3). That will help, afterwards, you only need to filter a Boolean input to a Boolean output. Sampling clock should be ~4x main frequency.

/odissey1

Perhaps you can help increase the hysteresis.

Filtering the digital signal is not hard. l built an excel model based on observing your operating frequencies, 5 kHz and 10 kHz.

Time base in usec.

Trace 1 is modulating data

Trace 2 is FSK signal

Trace 3 is delayed FSK signal

Trace 4 is XOR of 2 and 3, what you want to filter. The duty cycle changing with delay is obvious.

Trace 5 is an RC-filtered version (done here with a software IIR filter)

The comparator is sampled every 20 usec (set up a timer interrupt to do this)

Set up a software counter. When comp out = 1, and count < 32, increment counter.

When comp out = 0, and count not equal 0, decrement counter.

Trace 6 is the counter result.

Set comparison at mid-scale (16). If count > 16 set output high, if <16 set output low.

Write output to a pin, connect pin to UART.

The interrupt load is minimal, it takes only a few instructions, maybe on a few percent interrupt load.

You can easily add hysteresis.

Another issue: You waveform looks terrible at the higher frequency:

It looks like your sine table is not aligned properly,