I'm currently in a concept design stage for a painfully miniaturised device! I haven't got round to PCB design yet and haven't got any prior experience with board design yet.
A lot of my concepts require flex PCB with some fairly sharp bends, as I need to route a lot of capacitive sensors to the periphery of my device. Since 2 sided flex allows sharper bends than multilayer flex I was wondering how easy it was to route the WLCSP PSoC 63 with only 2 layers, the flexible routing makes me think some clever arrangement or pins would often allow this, but obviously its one of those things you have to try first before you know for sure so I was wondering what other peoples experience was for the smallest PSoC packages in general.
I figured its one of those questions that is quick to give helpful advise on for some one who has already done it, but could save me a lot of time as it would allow me to make some good pre-emptive design decisions based on the minimum bend radiuses.
Also if I have missed/unaware of some better alternative approaches you think might apply to my design please let me know, e.g. using 4 layer and reducing to 2?
Also on another note I'm trying to route 48 capacitive sensor plates to the periphery so what kind of minimum trace pitch can I expect for a consumer priced product?
If its helpful I don't have much other design specific routing besides 2-3 i2c devices powered from PSoC pins, and 4 intsances of iDAC/ADCs combos for resistance measuring and a chip antenna.