Both the TRMs do talk about the same thing.
The figure in Architecture TRM talks about the max possible protection context supported in the architecture, which is 16 (hence [15:1] + PC#0). However in PSoC 62/63 family, the number of available protection contexts is 8 (PC#7 to PC#0).
The register definition in Register TRM talks about the available PC bits in the PSoC 62/63 family. PC_MASK_15_TO_1[15:9] means bits [15:9] of the PROT_SMPU_SMPU_STRUCT0_ATT0 register holds the LSB 7 bits (PC#7 to PC#1) of PC_MASK_15_TO_1. The MSB 8 bits of PC_MASK_15_TO_1 (PC#15 to PC#8) is not implemented in PSoC 62/63 family and hence are not shown in registers TRM.
The [15:9] notation does not denote the bits of PC_MASK_15_TO_1 field but rather it denotes the bits [15:9] of the PROT_SMPU_SMPU_STRUCT0_ATT0 register.
Hope this clarifies your question - let me know if you need further clarification.
Meenakshi Sundaram R