2 of 2 people found this helpful
Yes this is possible, but it is not a "supported" feature. What I mean is you are own your own when using it, there is no official Cypress support for it. That being said I don't suspect there will be any issues.
Here is what you need to do.
1. In the project, click on the components tab (this is the vertical tab list in the workspace explorer)
2. Right click on your project and select Import Component...
3. On the upper drop down select CyComponentLibrary
4. In the drop down below that select ADC_SAR_SEQ_P4_v2_50
5. Click OK.
6. DO NOT rename the component. If you do then the component won't build and there will be all kinds of issues. If you want to rename then a bunch of files need to be changed. It is possible to rename just really annoying
7. Open ADC_SAR_SEQ_P4_v2_50.cysch, and open page 1 tab
8. On the right hand side of the cy_psoc4_sar primitive you will see a data[11:0] and data_valid outputs.
9. Connect digital output terminals to these terminals. The digital output terminal can be found on the left side of the schematic, They are green arrows with "D" above them. Give them whatever name you'd like. Double click the output connected to data[11:0] and select the "Bits Range" radio button. set the left index to 11 and the right index to 0.
10. Open ADC_SAR_SEQ_P4_v2_50.cysm add Digital Output Terminals with the same names as the digital outputs terminals you used in the .cysch. Again make sure the bit widths are set correctly.
11. Save your project. Now the ADC on your project schematic should have the digital outputs available.
12. Now on your project schematic you can route those digital outputs to digital logic.
1 of 1 people found this helpful
way back I modified SAR_ADC with parallel ouput for PSoC5
I am not sure if ADC_SAR on PSoC4 has same internals, if so use it as reference
Great answer! Can I use EOC or another signal to clock the digital output of the ADC? In other words, how do I know I have fresh data for the UDB?
In PSoC5 the 'eos' comes right after ADC conversion is completed, while eoc may appear over then a microsecond later. So bus data should be sampled on eos.
Not sure what can be accomplished on PSoC4 with digital output bus, it practically has no UDB.