1 Reply Latest reply on May 15, 2018 5:44 AM by MeenakshiR_71

    Why can the compare be higher than the period for a PWM?

      I am trying to make an equivalent design from my PSoC4 PRiSM by using the Pseudo Random configuration on the PWM in PSoC6 (its purpose is to be able to dim an LED without the apparent effect of blinking)
      What is odd is that I can't seem to get the output pattern to work correctly, and for some weird reason I am able to set the compare value to be higher than the period value, and begin to see a pattern that is closer to what I imagine it should be. I used a logic analyzer to confirm that the signal is closer to what I want, but I don't believe I should be able to set the compare to be higher than the period. Is there some sort of bug? Or am I misunderstanding something? I've attached a screenshot of what I'm seeing

        • 1. Re: Why can the compare be higher than the period for a PWM?

          Hello benec_3294706,


          It appears like a bug in our component customizer (the diagram shown is wrong). Thanks for pointing it out - I will file a defect ticket to get it corrected.


          The behavior of the TCPWM block in Pseudo random mode can be understood from the Device Architecture TRM (Section 27.3.6).


          In summary, the PRS mode does not use the period register to reset the counter. The period register is only used to generate an interrupt (TC) when the counter equals the period register value. The counter uses either a 16-bit or a 32-bit LFSR (depending on the resolution selected) to determine the next counter value (thus giving the counter a Pseudo random nature). The compare operation simply sets the output if the current counter value is less than the compare value and clears otherwise - thus giving the output waveform a pseudo random nature.


          Let me know if this helps or if you have further queries.



          Meenakshi Sundaram R