1 Reply Latest reply on May 8, 2018 5:08 AM by srdr

    we are getting fx3 watermark flag changes with different clocks

    eiekarthick_3359826

      we are getting fx3 watermark changing with different clocks. We are setting watermark as 10 in fx3 side with 32 bit FPGA interface.

      At 100MHz PCLK, we are getting expected frames in the receiver side.

      If we decrease the frequency (70 MHz), we are required to supply one more extra data.

       

      As we understood, whenever we change the FX3 clock, we need to tune the data count to be sent after the flagb is low for the same watermark value.

       

      In our case,

       

      We are setting watermark value as '10' and sending watermark x (32/bus width) – 4  = 6 for 100 MHz

       

      For 70 MHz interface we can get the frame only if we send one more data (7 data's after flagb low).

       

      We are using sp601 and superspeed explorer kit

       

      Kindly help us to understand about this issue.

       

      Regards,

      Karthick M

      FPGA DESIGN ENGINEER,

      E-CON systems india pvt ltd,

      Chennai. India

        • 1. Re: we are getting fx3 watermark flag changes with different clocks
          srdr

          Karthick,

           

          As per your description, when the water mark flag is asserted, the buffer has 28 bytes space (so you need to send 7 data words to fill the buffer) but in case of 70 MHz. But in case of 100 MHz, it has 24 bytes space (sending 6 data words filling the buffer).

           

          Create a small buffer (1K size) and test the functionality at 100MHz and 70 MHz.

          Share the screen shots of the control signals along with the Flags in both the cases.

          We can cross check whether the above said behavior is matching in the timing diagram.

           

          Regards,

          Sridhar