4 Replies Latest reply on Jun 2, 2018 7:23 AM by rajivv_36

    unusual high ADC offset in PSoC1 CY8C24123A

      I have a quite simple device, consisting of PSoC1 with 2 analogue signals (0...3.3V) connected to P0_2 and P0_4 (high-Z analog input).

      Then these signals are fed via AMUX4 and PGA (gain=1) to lets say ADCINCVR.

      Via EzI2C the results are monitored on a Display.

       

      The ADC is configured according to datasheet/example code for 0...3.3V input range with Refmux (Vdd/2)+/-(Vdd/2).

       

      Problem: No matter, which type of ADC-block I am using (EzADC, ADCINC12, ADCINC, ADCINCVR, DELSIG) I get

      unusual high zero-voltage readings with all of them exceeding the datasheet values by far.

       

      While the datasheet says 3...10 mV offset (depending on type) all the time I see 40...60 mV Offset, regardless of the ADC-type used.

      For instance the ADCINC and ADCINCVR give ~80 count reading for 0V input, see following results.

      sensor.png

      For each of the ADC blocks I have played around with clocks, offset, timing to no avail.

       

      Comparing this with the 10-Bit AVR/Arduino ADC on must state that the PSoC1 performs worse.
      Ist there something I can do, or are the datasheet values for ADC offset wrong or to be interpreted differently?

       

      Most ADC blocks require the PGA block to be able to route the pins - maybe the offsets of PGA and ADC

      add up badly?

       

      Any Idea, even any confirmation of that behaviour is welcome.

      Regards, Stefan

        • 1. Re: unusual high ADC offset in PSoC1 CY8C24123A

          Simpler question: can somebody confirm or disprove that the CY8C24123A has such an zero-offset for single-ended signals?

           

          I have put an arduino in parallel and what did it show:

          ==> expected behaviour, no noticeable offset.....

          • 2. Re: unusual high ADC offset in PSoC1 CY8C24123A

            Hi Stephan,

             

            The offset is probably due to the PGA output voltage swing. It is between 50mV to VDD-50mV. if possible, can you clamp the input signal to mid rail? The other option is to connect the ADC input directly to the pins, bypassing the PGA if no gain is required.

             

            In general, to correct the error in reading because of offset in the signal chain, "correlated double sampling" can be used. Refer application note AN2226  for details - http://www.cypress.com/documentation/application-notes/an2226-psoc-1-using-correlated-double-sampling-reduce-offset-drif…

             

            -Rajiv

            • 3. Re: unusual high ADC offset in PSoC1 CY8C24123A

              Hello Rajiv,

              thank you for answering.

               

              Indeed, the signal is directly wired to the input pins. The problem is: in Designer I can

              not route the signal to the ADC block without using the PGA block. I do not require the
              PGA for amplification - it seems to be required just for routing in Designer.

               

              The only way I found to route the two input signals to the ADC block is via the

              AMUX4 block and the PGA block. As I said, the PGA is not required but I found

              no way to omit it in PSOC1. Maybe I understood something wrong?

               

              I can load up the designer sketch on Monday if that clarifies the problem.

              Regards, Stefan

              • 4. Re: unusual high ADC offset in PSoC1 CY8C24123A

                Hi Stephan,

                 

                I see the restrictions in the selected device. I would suggest, adding a bias to the input signal as shown here-

                 

                SignalBias.jpg

                The above circuit will lift your measurement signal above the lower limit of PGA output voltage swing specification. Also, it will provide necessary scaling so as to support entire input range. Is your input signal also derived from VDD? If yes, then this forms a ratiometric measurement, eliminating the dependency on VDD.

                 

                For correcting the offset from PGA and ADC, here is what I suggest-

                1. Before measuring the input signal, in run time, configure the PGA input to connect to AGND.

                2. Measure the PGA output using ADC, which gives the PGA and ADC offset combined. You will have to work on proper correction depending on whether the ADC result format is kept signed or unsigned.

                3. Then configure the PGA input to connect to the input signal

                4. Measure using ADC

                5. Subtract the measured offset from step 2.

                 

                However, the accuracy of offset measurement in the signal chain, depends on the value of VDD (as REFMUX is set to VDD/2+/-VDD/2). So, it needs to be done every time the input signal is required to be measured. If VDD is fairly constant, you can measure the offset only once. 

                 

                Also, watch out for the output impedance of the input signal source. it will be one source of error in the measurement. 

                 

                Hope this helps for your application.

                 

                -Rajiv