May I ask for more information.
What kind of signal do you want to synchronize?
Any timing restrictions? How long is the pulse you need to identify?
Basically the clocks are in synch already as the default clock source used to generate all the clocks in the UDBs is Clk_peri which is derived from Clk_HF0 that also sources the M4 core (Clk_Fast). If it is greater than 100MHz then Clk_Peri has to be divided by 2.
Ok UDB is Universal Digit Blocks, correct? The graphic above shows a PLL output used by the M4 core. However, it is showing 100MHz and I thoughtM4 core was 150MHz (from the Datasheet). Second, what is Clk_Peri? This is shown in the above graphic as the M4 clock after a /2 divider. I assume it is clock peripheral. Does this mean I synchronize to it? I grab a Sync block and the clock for the Sync block is Clk_Peri?
Also, it could be that I don't need a synchronizer, because all input are already synchronized to the processor clock and metastability is already minimized. The status register shows a clock. What is it for?
I have attached a schematic showing a sync block for each input. I am hoping this is not necessary.
Yes, UDB = Universal Digital Block.
Clk_Peri is the clock that is the default reference being used in the schematic view. So yes, to your description.
So synchronisation should not be needed.
The Clock of the Status registers is used if the bits in the register are used in "sticky" instead of "transparent" mode. In "sticky" mode the input is sampled on rising edge of that clock and only cleared when the register is read.
PS: Yes, 150MHz is the max. of the M4 core, above are just the default values and they can be updated in the "Design Wide Resources" "Clocks" Tab.