3 Replies Latest reply on Apr 23, 2018 10:10 AM by user_342122993

    UDB: generate ready signal when arithmetic/logic function finishes

    user_246598725

      Hi,

       

      perhaps a dumb question:

      I'm modifying the parallel in/out example from AN82156 to have an UDB based adder with two parallel 8-bit inputs and carry in/out. This should be no problem, but I also need an operation result ready signal. How to generate this?

      The current implementation has only two states: the idle state(1b0), which loads PI to A1, and the add state (1b1, forced by a rising edge on a trigger input), which adds the PI/A0 value to A1 and outputs the ALU result to PO. Now, how to generate the ready signal? If I use the state value as a ready signal, I think it's rising too early, because the datapath needs some time. Or should the ready signal equal to the inversion of the state bit, so that the ready state is signalled when the state machine is in idle state?

       

      Regards