I believe you can use the state signal changing 1 to 0 as a ready signal.
thank you for your answer, it works to have the ready signal extracted out of the state signal. However, I have to revert my statement that it should be no problem to get the adder to work It seems that I can't get the routed carry input to work properly.
CI_SELA is set to ROUTE, and in the verilog file the .CI_ROUTE input is set to a registered carry input signal of the module. The carry input is registered when the state machine is instructed to run. Any ideas what's going wrong?
Can you post the component?