A look into the counter datasheet, AC specs show that for the FF implementation the max frequency is 67 MHz.
The explanation of th clock input shows that for the UDB implementation the clock input is used for detecting changes of the count input.
Can I use a counter (fixed function or UDB) in PSOC5 with clock frequency of 60MHz while at the same time the CPU (and all the other peripherials) run with 10 MHz clock ?(in order to save power).
The UDB runs on bus clock. I believe that is is not possible to run CPU slower than UDB.
CPU clock can run at lower clock than UDB clock.
As UDB clock is synchronized with Master clk and Bus_clk (CPU Clock) is obtained by dividing the Master clock in .cydwr.