2 Replies Latest reply on Apr 26, 2018 2:41 AM by vsrs

    Reset operation for CY8C4245PVI-482

    user_511731882

      Hi Team,

       

      Please let me know regarding reset operation of CY8C4245PVI-482.
      1) Is the state of GPIO pin "Hi-Z" at reset?

      2) Is the special procedure such as delay necessary for the reset pin sequence in the POR sequence at power-on?

       

      Is it OK at the same time that power-on and reset cancellation are performed during control?

      Or is there any need to delay anything?

      3) We are considering adding the damping resistance(1K ohm) and the capacitor (0.01 uF), but are there restrictions on the above power-on and reset sequence timing?

      4) I understand that "internal pull-up is effective", but is there any opinion that external pull-up is not necessary or not good?

      The customer would like to confirm whether there is a problem with only the resistance in the device.

       

      Thanks and regards,