5 Replies Latest reply on Apr 13, 2018 8:35 AM by e.pratt_1639216

    Two SPIs (One Master and One Slave) in PSoC4

    user_350540870

      I want to implement a project of two SPI Peripherals communicating with each other in a single PSoC4. As a first step, I will send a character string from Master to Slave and the Slave has to receive it correctly. I need help from someone who can give example code for this. Thanks in advance. Shaunak. https://tinu.live/

        • 1. Re: Two SPIs (One Master and One Slave) in PSoC4
          e.pratt_1639216

          I don't understand why you would want the two SPI modules on the same chip talking to each other...

          Anyhow, I gave it a shot for creating two SPI devices communicating with each other, and the fitter won't route the wires to each other.

          Not sure the IDE will let you wire the SPIs together internally.

          • 2. Re: Two SPIs (One Master and One Slave) in PSoC4
            user_350540870

            I have to use two SPIs talking to each other because I want to test PSoC4's SPI with my programming as I am doing SPI with PSoC4 and I have only one kit that is CY8CKIT-049 42xx. I do not have kit programmer, so I am programming the kit through the Bootloadable and UART Component Method. Whether I use UDB or SCB SPI, I get errors in both cases. This errors mainly generate because I am using three serial communication channels and hence clocks.(Please find attached herewith the snapshot of errors with SCB SPI.) The problem I am facing currently is I am not able to understand the messages the errors are conveying as there are not much details given. I need help in resolving these errors. Also, can someone help me to understand the component catalog (Given in Creator) of Cypress for different devices.

             

            SPI2_UART_BOOTLOADABLE_ERRORs.JPG

            Thanks in advance.

             

            Shaunak Agastya Vyas

            https://tinu.live/

            • 3. Re: Two SPIs (One Master and One Slave) in PSoC4
              e.pratt_1639216

              Hello Shaunak,

               

              The errors in the image you posted show that there are only two SPI peripherals, but you are trying to use 3, and thus it can't build it.

              Also, it is listing as needing more clocks to work; If you open the component and set the clock to be external, then create a "Clock" component on the schematic and wire it to the inputs of all of the SPI devices you might be able to fix the "too many clocks" issue.

              • 4. Re: Two SPIs (One Master and One Slave) in PSoC4
                user_350540870

                Hi e.pratt

                Please find attached herewith a snapshot. I kindly request you to see the TopDesign and Errors. Can you please explain how it is counting 7 Status Cells instead of 4?

                 

                Thanks in advance.

                 

                Shaunak Agastya Vyas

                https://tinu.live/

                 

                SPI2_UART_BOOTLOADABLE_ERRORs_1.JPG

                • 5. Re: Two SPIs (One Master and One Slave) in PSoC4
                  e.pratt_1639216

                  Hello Shaunak,

                   

                  The status cell count is related to the UDB (User Defined Block) which are general purpose circuitry used to implement hardware functions using verilog. The SPI components utilize theses UDB blocks to realize the SPI functionality without using CPU time/software code.

                  Each IC has a limited number of UDBs built into it at the factory, and the number is based on the specific chip. The chip you are designing for only has 4 UDBs that are Status Cells. The attached picture shows where you can look at the current project usage of the hardware resources in this respect.

                  Essentially, the SPI modules use 3 cells each, and the UART probably uses 1. But you should be able to see upon successful project build with the peripherals included.

                  There are multiple SPI peripheral modules defined, some of them may use less UDB cells (I have no idea which, if any, do)

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