Vcompliance of IDAC

[MiNe_85951]

The characteristics of Vcompliance is described in the IDAC data sheet of PSoC 4.

It is 0.8 V (min) even under sink / source conditions or 300 uA / 600 uA condition.

Does this mean that a voltage drop of 0.8 V will always be observed on the pin voltage when set to maximum current?

600 uA sink/source, 0.8 V Vcompliance(Drop voltage), The resistance value at that time corresponds to the translation 1333 Ohm.

300 uA sink/source, 0.8 V Vcompliance(Drop voltage), The resistance value at that time corresponds to the translation 2667 Ohm.

Do the above resistance component is affecting?

Please tell us the meaning of this spec.

[Anonymous]

I believe the 0.8V Vcompliance is the minimum voltage drop from the voltage power supply to the IDAC output. See this document for more information (not completely related): http://www.cypress.com/file/113026/download

The bottom of page 3 states:

The maximum voltage from the current source is the analog supply voltage (VDDA) minus the compliance voltage of the current source, typically less than a volt.

That statement makes me think the Vcompliance is referring to a voltage drop across the IDAC of what it can output for maximum voltage on the load.

[MiNe_85951]

Thank you for your answer.

I understood that a voltage drop will occur.
The reason why the voltage drop is the same even though the current value to be set is different,
Is it the diode component of the transistor used for the constant current circuit?

[Vasanth]

Hello Masashi san,

The compliance voltage or head room voltage in comes due to the fact that the MOS transistors should be in saturation for the circuit to work as expected. This is a general principle in mixed signal circuits. To satisfy this condition the the output voltage cannot move above this voltage level, as it will force the MOS devices to work out of saturation region.

Best Regards,
VSRS

[odissey1 · Accepted solution]

The compliance voltage of 0.8V means that max voltage produced by IDAC will be Vdda - 0.8V, no matter what current setting or load resistor. The IDAC is utilizing a current mirror topology, hence comes 0.8V loss on a transistor.

/odissey1

[MiNe_85951]

Thank you for your reply.

If the internal circuit is the current mirror, I understood this spec.