Which version of PDL you are looking at, and from which file you find that code snippet?
PDL 2.02 .
The fie is clk.c.
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The wait time settings will be written to each clock stabilization wait time register in the Clk_Init() function.
Each the setting become effective after enabling each clock.
In the Clk_EnableMainClock() function, the PDL sets MOSCE bit in SCM_CTL register to enable MainClock.
Then, the device will wait for a period specified in the Main clock stabilization wait time register.
The MORDY bit in the SCM_STR register will be set after internal counter reached to the specified period.