2 Replies Latest reply on May 17, 2018 8:40 PM by cheewooi.cheok_3277416

    HX2VL - Individual mode (pin 39) does not meet input low voltage requirement

    cheewooi.cheok_3277416

      Specified in data sheet: pull-down resistor of greater than 100k is required for individual mode (pin 39 of HX2VL)

      Also specified in data sheet: maximum leakage current is 10uA

      The maximum leakage current will result in 1V drop on the pull-down resistor. This 1V level might not be interpreted as logic low since input low voltage of 0.8V (max) is not met.

       

       

       

       

      In this case, what is Cypress recommendation to guarantee the design at worst case? 

       

      What will be the side effect if a pull-down resistor of let's say 75kR is used for Gang/Individual pin? 

       

       

      Kindly enlighten. 

       

       

       





       

        • 1. Re: HX2VL - Individual mode (pin 39) does not meet input low voltage requirement
          Madhu Lakshmipathy

          ‘Input leakage current’ is the current flowing to the chip I/O, when the corresponding I/O configured as input mode.

          This current will draw from external supply; or from another chip’s output connected to it.

          The leakage current will not flow through the pull-down resistor.

           

          Pull-down resistor will not draw current, as the pin is in input mode. The IC pins shall drive in output mode only.

          Since the pin in input mode, and not drawing current, this pin value to be read as near zero.

          If you have a DVK, you can identify this resistor, and take measurement at pull-down resistor. I am sure it will be close to 0V.

          • 2. Re: HX2VL - Individual mode (pin 39) does not meet input low voltage requirement
            cheewooi.cheok_3277416

            Dear Madhu,

             

            Please see my comments to your replies below.

             

            There is definitely some leakage current flow through the pull-down

            resistor tied to Gang pin (Please refer to my comment 3 below about Ohm's

            law).

             

            I have only one question to Cypress: please provide an Absolute Value of

            what would be the Maximum leakage current flowing through the GANG pin at

            Worst Case that Cypress guarantee?

             

             

            Just sidetrack a bit: The SELFPWR pin is pulled-up to 5V with 510 kR

            resistor in DVK. This pin fulfills all you definition about leakage

            current: "it is the current flowing to the chip I/O" & "the current will

            draw from external supply".

             

            The same one question: what would be the Maximum leakage current flowing

            through the SELFPWR pin at Worst Case that Cypress guarantee?

             

             

            Thanks & Regards

            Cheok

             

            p/s: I have amended the title to "Individual mode (pin 39) might not meet

            input low voltage requirement at Worst Case to make my question clearer.