‘Input leakage current’ is the current flowing to the chip I/O, when the corresponding I/O configured as input mode.
This current will draw from external supply; or from another chip’s output connected to it.
The leakage current will not flow through the pull-down resistor.
Pull-down resistor will not draw current, as the pin is in input mode. The IC pins shall drive in output mode only.
Since the pin in input mode, and not drawing current, this pin value to be read as near zero.
If you have a DVK, you can identify this resistor, and take measurement at pull-down resistor. I am sure it will be close to 0V.
Please see my comments to your replies below.
There is definitely some leakage current flow through the pull-down
resistor tied to Gang pin (Please refer to my comment 3 below about Ohm's
I have only one question to Cypress: please provide an Absolute Value of
what would be the Maximum leakage current flowing through the GANG pin at
Worst Case that Cypress guarantee?
Just sidetrack a bit: The SELFPWR pin is pulled-up to 5V with 510 kR
resistor in DVK. This pin fulfills all you definition about leakage
current: "it is the current flowing to the chip I/O" & "the current will
draw from external supply".
The same one question: what would be the Maximum leakage current flowing
through the SELFPWR pin at Worst Case that Cypress guarantee?
Thanks & Regards
p/s: I have amended the title to "Individual mode (pin 39) might not meet
input low voltage requirement at Worst Case to make my question clearer.