Specified in data sheet: pull-down resistor of greater than 100k is required for individual mode (pin 39 of HX2VL)
Also specified in data sheet: maximum leakage current is 10uA
The maximum leakage current will result in 1V drop on the pull-down resistor. This 1V level might not be interpreted as logic low since input low voltage of 0.8V (max) is not met.
In this case, what is Cypress recommendation to guarantee the design at worst case?
What will be the side effect if a pull-down resistor of let's say 75kR is used for Gang/Individual pin?
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