I have to write a VHDL to interface my FX3 with an FPGA. I loaded the disc image AN65974 (slave fifo sync 2 bit) in the ram but i can't understand the endpoint addresses (flagA and FlagB). What they are? 00 - 01 - 10 - 11 ?
The flag A and Flag B are Thread 0 DMA ready and Thread 0 DMA Watermark flags respectively. You have to drive the address 00 in the 2 bit address bus to select Thread 0 and the corresponding socket status will be reflected by Flag A and Flag B.