SRAM on the explorer kit is interfaced with FX3 over GPIF II interface. The READ and WRITE to/from SRAM is done using the GPIF state machine which is designed for FX3 to communicate with the SRAM. The FX3 GPIF state machine generates READ and WRITE signals which enables the SRAM to move data IN and OUT.
Sorry I think I may have skipped over my main point. Basically, is the SRAM part of the DMA buffers that are used for the exchange of data between the FX3 and any peripheral. For example would I need to include SRAM in my design if I intend on using the FX3 as a FIFO slave (like in AN65974) to move data between my PC software and a FPGA?.
SRAM on SuperSpeed explorer kit is not needed if you are using FX3 as slave FIFO for above mentioned application. Jumper J5 is used to enable/disable SRAM on the kit.
I thought this might be the case. Thanks for the quick reply!