1 Reply Latest reply on Apr 3, 2018 9:29 AM by ZhiF_31



      I'm trying to adapt the code provided in an old application note CY3686 to a new NAND Flash device.

      The code uses up to 4K-page, but the NAND Flash chip has 16K-page.

      I've some difficulties to understand how to change the code to align with the new NAND addressing physical cycles (5 address cycle scheme).

      Also translation of the Logical to Physical addresses is not totally clear to me, basically the way the code operates a block erase.

      My platform is a compatible FX2LP board, equipped with CY7C68013 USB2.0 front end.

      Any inputs are welcome.