We speculate that the AN 68272 covers a low baud rate and thus increases this waiting time "CyDelay (UART_BYTE 2 BYTE_TIME_OUT);".
It is best to tell us the reason why it is set to 25 ms.
If it is not possible, please tell us the recommended waiting time for the baud rate.
19200 bps, AA ms.
38400 bps, BB ms.
57600 bps, CC ms.
Hello Mineda-san, Byte to Byte time out for detecting end of block data from host. This has to be set to a value which is greater than the expected maximum delay between two bytes during a block/packet transmission from the host. User needs to account for the delay in hardware converters while calculating this value, if you are using any USB-UART bridges. Regards, Geon
Thank you for your reply.
We wondered that a very long timeout was set.
I understand why the timeout is set to 25 ms in your explanation.
We don't use the USB-UART bridge, and communication between the host and the PSoC 5 LP is using UART only.
Since the baud rate is 57600 bps.
It was judged that there is no problem even in 2 ms.
As a precaution we will try shorten this timeout and confirm for the current margin.
Byte-to-byte intervaltime interval is defined as the time consumed to transfer two data elements with selected data rate. For more details make use of section: SCB_CyBtldrCommRead details of PSoC 4 SCB datasheet.
For 57600 bps, 1 bit takes ~17.3 us. Consider 20 bits or 2 bytes transfer (2* (8 bits + Start bit + Stop bit) ) , so SCB_UART_BYTE_TO_BYTE = 17.3 ms * 20 = ~346 us.
In PSoC 4 SCB based UART, it is calculated by the component based on current data rate selection unlike UDB based UART. Another alternative is to use SCB_PSoC4 in bootloader project to get value of SCB_UART_BYTE_TO_BYTE (*_BOOT.h file) and then use it for UART(UDB based). However, you need to convert it to closest mS value. In above example it would be 1ms. Hope this helps.
Thank you for detailed calculation results.
I understood well why the timeout was set for a long time.