2 Replies Latest reply on Mar 27, 2018 6:04 PM by kegr_3255171

    QSPI Flash mode bits

      I am using 2x S25FL512S QSPI flash chips. In the Cypress data sheet, it mentions mode bits following the address for several of the read commands. I couldn't find any explanation of values for these bits in the DS other than 0x5a to extend continuous read cycles. What are these mode bits for and what other values are there?

        • 1. Re: QSPI Flash mode bits

          I was wondering the same thing when I encountered the same thing in the S25FS512S datasheet. The two devices (and datasheets) are similar enough.


          Under both the 'Dual I/O Read' and 'Quad I/O Read' command sections, the datasheet states that to imply the next command instruction is the same as the current one, the mode bits must equal 'Axh'. To clarify, 'Axh' means the upper nibble (bits 7-4) must equal 'Ah' and the lower nibble (bits 3-0) can be anything.


          And under the 'DDR Dual IO Read' and 'DDR Quad I/O Read' command sections, the datasheet states that the mode bits are similarly used except with the requirement that the upper and lower nibbles must be complementary.


          Note that the values of the mode bits differ depending on which set of instructions you are using.

          • 2. Re: QSPI Flash mode bits

            I'd be really surprised (and disappointed) if that is the only use of the mode bits. I did read the data sheet for an ISSI DDR part and it says pretty much the same thing - "If the mode bits=AXh (where X is don’t care), it can execute the AX read mode (without command). When the mode bits are different from AXh, the device exits the AX read operation".  Micron doesn't even mention mode bits