1 Reply Latest reply on Mar 27, 2018 6:43 PM by RuzheZ_36

    PSoC4L - I2C Master, SCB clock freeze


      PSoC4 chip CY8C4247AZI-L485, I2C master transfer (write) to 24C04 EEPROM memory (ST chip M24C04WMN6).

      I found that I2C Master component add random delay time between 5..50ms when execute I2CMasterSendStart() function.

      This demo project has wired EEPROM memory but in end user application (without EEPROM memory) this behavior also exist.

      This issue isn't linked with EEPROM.


      Logic analyzer shows I2CMasterSendStart() transfer. Last bit before ACK is delayed (level low) in this case it takes 55ms.


      This show, first transfer has delay (approx 50ms) , second transfer is correct, third transfer also has delay (59ms)

      In my opinion this is SCB I2C fixed block issue. In end user application this issue delay all I2C transfers about 500ms.



      How to eliminate delay in I2CMasterSendStart() transfer?


      As a reference the same PSoC project I run at CY8C4245AXI-L483, all works correctly.


      Best regards,

      Zbigniew Kuczbanski



      1. PSoC4L_I2CM_4247.cyprj.Archive01.zip - ready to use project for CY8C4247AZI-L485. It's fully repetitive.

      2. PSoC4L_I2CM_4245.cyprj.Archive01.zip - the same source code for CY8C4245AXI-L483. All works correctly,  only for reference purpose.


      uint32_t I2CWriteN(uint8_t ui8I2CAddr, uint8_t ui8RegAddr, const uint8_t *ptrui8Data, uint32_t ui32Len, uint32_t ui32I2CTimeout_ms)


          uint32_t ui32Result;



          while (ui32Len--) {





          return (ui32Result);