First of all, the 5 bus masters available in PSoC 6 are CM4, CM0+, Crypto, DW0 and DW1. Test controller is a bus master but that is of not much use to a customer.
Now, there is a very subtle difference in the definition of DataWire (DW) and Direct Memory Access (DMA). Essentially DWs are primarily referenced in the context of Memory to/fro Peripheral transfers and DMAs are primarily referenced in the context of Memory to Memory transfers. Though both function the same (without much difference), the primarily application they are targeted for, reflect the naming.
Now PSoC 6 implements DWs (not DMAs - remember they are the same but primary application define the naming) as their primary task is to transfer data between memory and peripherals. However, datawires can perform memory to memory transfers as well.
PSoC 6 has two DW blocks, which means it can perform two independent and simultaneous transfers using these two blocks. Each DW supports up to 16 channels - total 2x16 = 32 channels and at any time only one channel can be active within a DW (decided by a priority).
Let me know if this helps.
Meenakshi Sundaram R