3 Replies Latest reply on Mar 28, 2018 6:11 PM by xieyuanlu_3250341

    Question about the Timing Check of S29AL016J simulation model

    xieyuanlu_3250341

      Hi there, I'm currently using Spansion (now Cypress) S29AL016J simulation model (which was downloaded at official site: http://www.cypress.com/simulation-models) in our design. Filename of the model is "s29al016j.v". In our simulation, I found something strange about the model:   During CENeg = 1 (viz, chip is NOT selected), some togglings on WENeg and A19~A0 may trigger timing violation, for example: ====== "../../ext_modules/emc_memories/S29al016j/model/s29al016j.v", 1116: Timing violation in tbench.u_emc_flash     $hold( negedge WENeg &&& Check:1494554100000, A10:1494554100000, limit: 45000000 ); "../../ext_modules/emc_memories/S29al016j/model/s29al016j.v", 1111: Timing violation in tbench.u_emc_flash     $hold( negedge WENeg &&& Check:1494752600000, A5:1494752600000, limit: 45000000 ); ====== In my understanding, when chip is deselected, all other signals including WENeg, Address, are don't care, and toggling on these signals should NOT trigger timing violation. However, my simulation shows otherwise. Can anyone please show me whether I can ignore this timing violation? thx & BR~~