3 Replies Latest reply on Mar 22, 2018 2:34 PM by buha

    S29GL01GP11TFI02 Gives No Joy

    johnschulte

      Recently we had to migrate from J3 flash to S29GL on several of our products, our first PWB (re-laid out to accommodate the 56-pin tssop pinout difference) is back with the S29GL installed, we cannot get the flash to do anything.  Here's all we've tried so far:

       

      • Verified schematic and PWB footprint for the umpteenth time, fresh eyes confirmed all is correct.
      • Vcc = Vio =3.3V
      • Flash reset signal (net nconfig on schematic) from the CPLD was not conforming to data reset requirements at power up, inclusion of power supervisor made the reset compliant (>35 us from Vcc min).  3.3V ramp time is measured as 7 ms.
      • CPLD flash reset signal (f_rpn) is connected to flash’s write protect (ACC/WP#) pin and toggling at power up, this may or may not be an issue (the data sheet says nothing about the state of this pin at power-up), created a new CPLD load that holds this pin inactive (high).
      • S29GL flash data sheet says “Writing incorrect address and data values or writing them in an improper sequence may place the device in an unknown state”.  Upon FPGA configuration a “FF” command is written to the flash (initiated by the FPGA) and then the capability information is read from the flash and loaded into registers in the FPGA.  This command placed the old J3 flash into read array mode, it is an undefined command for the S29GL flash.  The FPGA firmware was changed (v6bDEAD.sof), now the firmware sends a “F0” command which is a reset to the S29GL (it was initially desired to just eliminate the command being issued but the firmware is a bit impenetrable, quicker and easier to change the command).  It was verified that the 3 lsb’s changed from all 1’s (with the released firmware) to all 0’s (v6bDEAD.sof) during the initial write command after FPGA configuration between the two FPGA firmware version so it’s thought the “F0” is being issued with the modified firmware.
      • Write timing – 35ns min pulse width required, 75 ns measured
      • Read timing – read access time is 110ns, we are 362 ns (CE# & OE# both asserted for this time).
      • Unable to read manufacturer ID, tried to send command Chip Erase command (using both the full six cycle command and the shorter Unlock Bypass two cycle command) in an effort to make the busy signal (RY/BY# pin) go active indicating some sort of function from the part, no luck.
      • Read app note (AN201311) describing migration from J3 to S29GL devices, nothing new there.
      • Read app note (AN99123) describing reset voltage and timing requirements for S29GL, we comply.
      • Tried two different boards- no difference

      So any suggestions would be appreciated.